| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.16 2003/04/09 16:24:03 simont
|
|
// change wr_sft to 2 bit wire.
|
|
//
|
// Revision 1.15 2003/04/09 15:49:42 simont
|
// Revision 1.15 2003/04/09 15:49:42 simont
|
// Register oc8051_sfr dato output, add signal wait_data.
|
// Register oc8051_sfr dato output, add signal wait_data.
|
//
|
//
|
// Revision 1.14 2003/01/13 14:14:40 simont
|
// Revision 1.14 2003/01/13 14:14:40 simont
|
// replace some modules
|
// replace some modules
|
| Line 118... |
Line 121... |
|
|
//
|
//
|
// state if 2'b00 then normal execution, sle instructin that need more than one clock
|
// state if 2'b00 then normal execution, sle instructin that need more than one clock
|
// op instruction buffer
|
// op instruction buffer
|
reg [1:0] state;
|
reg [1:0] state;
|
|
wire [1:0] state_dec;
|
reg [7:0] op;
|
reg [7:0] op;
|
wire [7:0] op_cur;
|
wire [7:0] op_cur;
|
reg [2:0] ram_rd_sel_r;
|
reg [2:0] ram_rd_sel_r;
|
|
|
reg stb_i;
|
reg stb_i;
|
|
|
assign rd = !state[0] && !state[1] && !wait_data;// && !stb_o;
|
assign rd = !state[0] && !state[1] && !wait_data;// && !stb_o;
|
|
|
assign istb = (!state[1]) && stb_i;
|
assign istb = (!state[1]) && stb_i;
|
|
|
|
assign state_dec = wait_data ? 2'b00 : state;
|
|
|
assign op_cur = (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
|
assign op_cur = (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
|
|
|
assign op1_c = op_cur[2:0];
|
assign op1_c = op_cur[2:0];
|
|
|
| Line 143... |
Line 147... |
assign wr_o = wait_data ? 1'b0 : wr;
|
assign wr_o = wait_data ? 1'b0 : wr;
|
|
|
//
|
//
|
// main block
|
// main block
|
// unregisterd outputs
|
// unregisterd outputs
|
always @(op_cur or eq or state or mem_wait)
|
always @(op_cur or eq or state_dec or mem_wait)
|
begin
|
begin
|
case (state)
|
case (state_dec)
|
2'b01: begin
|
2'b01: begin
|
casex (op_cur)
|
casex (op_cur)
|
`OC8051_MOVC_DP :begin
|
`OC8051_MOVC_DP :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
| Line 245... |
Line 249... |
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_R : begin
|
`OC8051_CJNE_R : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_I : begin
|
`OC8051_CJNE_I : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_D : begin
|
`OC8051_CJNE_D : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_C : begin
|
`OC8051_CJNE_C : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JBC : begin
|
`OC8051_JBC : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JC : begin
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
|
pc_wr = eq;
|
|
pc_sel = `OC8051_PIS_ALU;
|
|
comp_sel = `OC8051_CSS_CY;
|
|
rmw = `OC8051_RMW_N;
|
|
stb_i = 1'b1;
|
|
bit_addr = 1'b0;
|
|
end
|
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_ALU;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
| Line 335... |
Line 330... |
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JNC : begin
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
|
pc_wr = !eq;
|
|
pc_sel = `OC8051_PIS_ALU;
|
|
comp_sel = `OC8051_CSS_CY;
|
|
rmw = `OC8051_RMW_N;
|
|
stb_i = 1'b1;
|
|
bit_addr = 1'b0;
|
|
end
|
|
`OC8051_JNZ : begin
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
|
pc_wr = !eq;
|
|
pc_sel = `OC8051_PIS_ALU;
|
|
comp_sel = `OC8051_CSS_AZ;
|
|
rmw = `OC8051_RMW_N;
|
|
stb_i = 1'b1;
|
|
bit_addr = 1'b0;
|
|
end
|
|
`OC8051_JZ : begin
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
|
pc_wr = eq;
|
|
pc_sel = `OC8051_PIS_ALU;
|
|
comp_sel = `OC8051_CSS_AZ;
|
|
rmw = `OC8051_RMW_N;
|
|
stb_i = 1'b1;
|
|
bit_addr = 1'b0;
|
|
end
|
|
`OC8051_SJMP : begin
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
|
pc_wr = `OC8051_PCW_Y;
|
|
pc_sel = `OC8051_PIS_ALU;
|
|
comp_sel = `OC8051_CSS_DC;
|
|
rmw = `OC8051_RMW_N;
|
|
stb_i = 1'b1;
|
|
bit_addr = 1'b0;
|
|
end
|
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
| Line 1075... |
Line 1034... |
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JBC :begin
|
`OC8051_JBC :begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JC : begin
|
`OC8051_JC : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_PSW;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_CY;
|
comp_sel = `OC8051_CSS_CY;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
| Line 1108... |
Line 1067... |
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
|
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JNC : begin
|
`OC8051_JNC : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_PSW;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_CY;
|
comp_sel = `OC8051_CSS_CY;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JNZ :begin
|
`OC8051_JNZ :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_ACC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_AZ;
|
comp_sel = `OC8051_CSS_AZ;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JZ : begin
|
`OC8051_JZ : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_ACC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_AZ;
|
comp_sel = `OC8051_CSS_AZ;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
| Line 1426... |
Line 1386... |
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_SJMP : begin
|
`OC8051_SJMP : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_SUBB_D : begin
|
`OC8051_SUBB_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
| Line 1545... |
Line 1505... |
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end else if (!wait_data) begin
|
end else if (!wait_data) begin
|
case (state)
|
case (state_dec)
|
2'b01: begin
|
2'b01: begin
|
casex (op_cur)
|
casex (op_cur)
|
`OC8051_MOVC_DP :begin
|
`OC8051_MOVC_DP :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
| Line 1662... |
Line 1622... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
2'b10:
|
2'b10:
|
casex (op_cur)
|
casex (op_cur)
|
`OC8051_CJNE_R : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_CJNE_I : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_CJNE_D : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_CJNE_C : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_DJNZ_R : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_DJNZ_D : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JB : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JBC : begin
|
`OC8051_JBC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
| Line 1750... |
Line 1633... |
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JC : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JMP_D : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JNB : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JNC : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JNZ : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_JZ : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_SJMP : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
|
alu_op <= #1 `OC8051_ALU_NOP;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
| Line 1864... |
Line 1670... |
end
|
end
|
endcase
|
endcase
|
|
|
2'b11:
|
2'b11:
|
casex (op_cur)
|
casex (op_cur)
|
`OC8051_CJNE_R : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
|
alu_op <= #1 `OC8051_ALU_PCS;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_CJNE_I : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
|
alu_op <= #1 `OC8051_ALU_PCS;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_CJNE_D : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
|
alu_op <= #1 `OC8051_ALU_PCS;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_CJNE_C : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
|
alu_op <= #1 `OC8051_ALU_PCS;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_DJNZ_R : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
|
alu_op <= #1 `OC8051_ALU_PCS;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_DJNZ_D : begin
|
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
|
alu_op <= #1 `OC8051_ALU_PCS;
|
|
wr <= #1 1'b0;
|
|
psw_set <= #1 `OC8051_PS_NOT;
|
|
cy_sel <= #1 `OC8051_CY_0;
|
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
|
wr_sfr <= #1 `OC8051_WRS_N;
|
|
end
|
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
| Line 3105... |
Line 2845... |
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_SJMP : begin
|
`OC8051_SJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_PCS;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
| Line 3240... |
Line 2980... |
2'b11: state <= #1 2'b10;
|
2'b11: state <= #1 2'b10;
|
2'b00:
|
2'b00:
|
casex (op_in)
|
casex (op_in)
|
`OC8051_ACALL :state <= #1 2'b01;
|
`OC8051_ACALL :state <= #1 2'b01;
|
`OC8051_AJMP : state <= #1 2'b01;
|
`OC8051_AJMP : state <= #1 2'b01;
|
`OC8051_CJNE_R :state <= #1 2'b11;
|
`OC8051_CJNE_R : state <= #1 2'b10;
|
`OC8051_CJNE_I :state <= #1 2'b11;
|
`OC8051_CJNE_I : state <= #1 2'b10;
|
`OC8051_CJNE_D : state <= #1 2'b11;
|
`OC8051_CJNE_D : state <= #1 2'b10;
|
`OC8051_CJNE_C : state <= #1 2'b11;
|
`OC8051_CJNE_C : state <= #1 2'b10;
|
`OC8051_LJMP : state <= #1 2'b01;
|
`OC8051_LJMP : state <= #1 2'b01;
|
`OC8051_DJNZ_R :state <= #1 2'b11;
|
`OC8051_DJNZ_R : state <= #1 2'b10;
|
`OC8051_DJNZ_D :state <= #1 2'b11;
|
`OC8051_DJNZ_D : state <= #1 2'b10;
|
`OC8051_LCALL :state <= #1 2'b01;
|
`OC8051_LCALL :state <= #1 2'b01;
|
`OC8051_MOVC_DP :state <= #1 2'b11;
|
`OC8051_MOVC_DP :state <= #1 2'b11;
|
`OC8051_MOVC_PC :state <= #1 2'b11;
|
`OC8051_MOVC_PC :state <= #1 2'b11;
|
`OC8051_MOVX_IA :state <= #1 2'b10;
|
`OC8051_MOVX_IA :state <= #1 2'b10;
|
`OC8051_MOVX_AI :state <= #1 2'b10;
|
`OC8051_MOVX_AI :state <= #1 2'b10;
|
`OC8051_MOVX_PA :state <= #1 2'b10;
|
`OC8051_MOVX_PA :state <= #1 2'b10;
|
`OC8051_MOVX_AP :state <= #1 2'b10;
|
`OC8051_MOVX_AP :state <= #1 2'b10;
|
`OC8051_RET : state <= #1 2'b11;
|
`OC8051_RET : state <= #1 2'b11;
|
`OC8051_RETI : state <= #1 2'b11;
|
`OC8051_RETI : state <= #1 2'b11;
|
`OC8051_SJMP : state <= #1 2'b10;
|
`OC8051_SJMP : state <= #1 2'b01;
|
`OC8051_JB : state <= #1 2'b10;
|
`OC8051_JB : state <= #1 2'b10;
|
`OC8051_JBC : state <= #1 2'b10;
|
`OC8051_JBC : state <= #1 2'b10;
|
`OC8051_JC : state <= #1 2'b10;
|
`OC8051_JC : state <= #1 2'b01;
|
`OC8051_JMP_D : state <= #1 2'b10;
|
`OC8051_JMP_D : state <= #1 2'b10;
|
`OC8051_JNC : state <= #1 2'b10;
|
`OC8051_JNC : state <= #1 2'b01;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNZ : state <= #1 2'b10;
|
`OC8051_JNZ : state <= #1 2'b01;
|
`OC8051_JZ : state <= #1 2'b10;
|
`OC8051_JZ : state <= #1 2'b01;
|
`OC8051_DIV : state <= #1 2'b11;
|
`OC8051_DIV : state <= #1 2'b11;
|
`OC8051_MUL : state <= #1 2'b11;
|
`OC8051_MUL : state <= #1 2'b11;
|
default: state <= #1 2'b00;
|
default: state <= #1 2'b00;
|
endcase
|
endcase
|
default: state <= #1 2'b00;
|
default: state <= #1 2'b00;
|
