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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.11 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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Line 59... |
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module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
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module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
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wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
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wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
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pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
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pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
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rmw, stb_o, ack_i, wr_xaddr);
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rmw, stb_o, ack_i, wr_xaddr, istb, ea, iack);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// op_in (in) operation code [oc8051_op_select.op1]
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// op_in (in) operation code [oc8051_op_select.op1]
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// eq (in) compare result [oc8051_comp.eq]
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// eq (in) compare result [oc8051_comp.eq]
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Line 87... |
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
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// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
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// rd (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
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// rd (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
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// we_o (out) write to external rom [pin]
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// we_o (out) write to external rom [pin]
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// reti (out) return from interrupt [pin]
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// reti (out) return from interrupt [pin]
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// rmw (out) read modify write feature [oc8051_ports.rmw]
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// rmw (out) read modify write feature [oc8051_ports.rmw]
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// istb (out) strobe to instruction rom
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// ea (in) extrnal access
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// iack (in) scknowlage from external rom
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//
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//
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input clk, rst, eq, ack_i;
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input clk, rst, eq, ack_i, iack, ea;
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input [7:0] op_in;
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input [7:0] op_in;
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output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
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output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
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pc_wr, wad2, rmw, stb_o, wr_xaddr;
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pc_wr, wad2, rmw, stb_o, wr_xaddr, istb;
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output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
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output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
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output [2:0] ram_wr_sel, imm_sel;
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output [2:0] ram_wr_sel, imm_sel;
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output [3:0] alu_op;
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output [3:0] alu_op;
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output rd;
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output rd;
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reg reti, write_x, rmw, stb_buff, we_buff;
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reg reti, write_x, rmw, stb_buff, we_buff, istb_t;
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reg wr, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
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reg wr, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
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reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
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reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
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reg [3:0] alu_op;
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reg [3:0] alu_op;
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reg [2:0] ram_wr_sel, imm_sel;
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reg [2:0] ram_wr_sel, imm_sel;
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//
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//
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// if state = 2'b00 then read nex instruction
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// if state = 2'b00 then read nex instruction
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assign rd = !state[0] && !state[1] && !stb_o;
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assign rd = !state[0] && !state[1] && !stb_o;
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assign istb = (!state[1]) || istb_t;
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assign stb_o = stb_buff || stbw;
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assign stb_o = stb_buff || stbw;
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assign we_o = we_buff;
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assign we_o = we_buff;
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//assign we_o = write_x || we_buff;
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//assign we_o = write_x || we_buff;
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//
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//
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// main block
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// main block
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// case of instruction set control signals
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// case of instruction set control signals
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always @(op_in or eq or state or op or stb_o)
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always @(op_in or eq or state or op or stb_o or istb_t)
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begin
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begin
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if (stb_o) begin
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if (stb_o) begin
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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ram_wr_sel = `OC8051_RWS_DC;
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ram_wr_sel = `OC8051_RWS_DC;
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src_sel1 = `OC8051_ASS_DC;
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src_sel1 = `OC8051_ASS_DC;
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Line 3058... |
// in case of instructions that needs more than one clock set state
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// in case of instructions that needs more than one clock set state
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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state <= #1 2'b01;
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state <= #1 2'b01;
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else begin
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else if (istb_t && !iack) begin
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state <= #1 2'b01;
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end else begin
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case (state)
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case (state)
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2'b10: state <= #1 2'b01;
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2'b10: state <= #1 2'b01;
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2'b11: state <= #1 2'b10;
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2'b11: state <= #1 2'b10;
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2'b00:
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2'b00:
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casex (op_in)
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casex (op_in)
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we_buff <= #1 1'b1;
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we_buff <= #1 1'b1;
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end
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end
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end
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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istb_t <= #1 1'b0;
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else if (((op_in == `OC8051_MOVC_DP) || (op_in == `OC8051_MOVC_PC)) && !ea)
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istb_t <= #1 1'b1;
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else if (iack)
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istb_t <= #1 1'b0;
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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