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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Diff between revs 140 and 146
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| Rev 140 |
Rev 146 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2003/05/06 09:39:34 simont
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// cahnge assigment to pc_wait (remove istb_o)
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//
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// Revision 1.6 2003/05/05 15:46:37 simont
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// Revision 1.6 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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// add aditional alu destination to solve critical path.
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//
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//
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// Revision 1.5 2003/04/25 17:15:51 simont
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// Revision 1.5 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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// change branch instruction execution (reduse needed clock periods).
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assign ea_rom_sel = ea && ea_int;
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assign ea_rom_sel = ea && ea_int;
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assign wr_o = wr_i;
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assign wr_o = wr_i;
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assign wr_bit_o = wr_bit_i;
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assign wr_bit_o = wr_bit_i;
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assign mem_wait = dmem_wait || imem_wait;
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assign mem_wait = dmem_wait || imem_wait;
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assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
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assign istb_o = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
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assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
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assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
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assign wr_dat = des1;
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assign wr_dat = des1;
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