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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Diff between revs 116 and 117
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| Rev 116 |
Rev 117 |
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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/04/07 14:58:02 simont
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// change sfr's interface.
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//
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// Revision 1.9 2003/01/13 14:14:41 simont
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// Revision 1.9 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.8 2002/11/05 17:23:54 simont
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// Revision 1.8 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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input [7:0] wr_addr, data_in;
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input [7:0] wr_addr, data_in;
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output [1:0] bank_sel;
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output [1:0] bank_sel;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data;
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reg [7:1] data;
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wire wr_psw;
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wire wr_psw;
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assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
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assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
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assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
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assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
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assign data_out = data;
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assign data_out = {data[7:1], p};
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//
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//
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//case writing to psw
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//case writing to psw
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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data[2] <= #1 ov_in;
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data[2] <= #1 ov_in;
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end
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end
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endcase
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endcase
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end
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end
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data[0] <= #1 p;
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end
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end
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end
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end
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endmodule
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endmodule
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