| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/04/07 13:29:16 simont
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// change uart to meet timing.
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//
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// Revision 1.5 2003/04/04 10:35:07 simont
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// Revision 1.5 2003/04/04 10:35:07 simont
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// signal prsc_ow added.
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// signal prsc_ow added.
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//
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//
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// Revision 1.4 2003/03/28 17:45:57 simont
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// Revision 1.4 2003/03/28 17:45:57 simont
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// change module name.
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// change module name.
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| Line 157... |
Line 160... |
reg bit_out;
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reg bit_out;
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reg [7:0] dat0, adr0_r;
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reg [7:0] dat0, adr0_r;
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|
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reg wr_bit_r;
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reg wr_bit_r;
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reg [2:0] ram_wr_sel_r;
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reg [2:0] ram_wr_sel_r;
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wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit, pca_bit;
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|
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//sfr's
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wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit;
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|
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wire p, int_uart, tf0, tf1, tr0, tr1;
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wire p, int_uart, tf0, tf1, tr0, tr1;
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wire dps, rclk, tclk, brate2, tc2_int;
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wire rclk, tclk, brate2, tc2_int;
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wire [7:0] b_reg, psw, ports, uart, int_out, tc_out, tc2, sp_out;
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wire [7:0] b_reg, psw,
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//ports
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p0_data, p1_data, p2_data, p3_data,
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//interrupt control
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ie, tcon, ip,
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// t/c 2
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t2con, tl2, th2, rcap2l, rcap2h,
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// t/c 0,1
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tmod, tl0, th0, tl1, th1,
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// serial interface
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scon, pcon, sbuf,
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// stack
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sp_out;
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wire pres_ow;
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wire pres_ow;
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assign cy = psw[7];
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assign cy = psw[7];
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assign srcAc = psw [6];
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assign srcAc = psw [6];
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| Line 174... |
Line 193... |
//
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//
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// accumulator
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// accumulator
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// ACC
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// ACC
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oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
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oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
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.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
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.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
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.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p));
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.wr_addr(adr1), .data_out(acc), .p(p));
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|
|
|
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//
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//
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// b register
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// b register
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// B
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// B
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oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),
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oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0[2:0]),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
|
.data_out(b_reg), .wr_sfr(wr_sfr));
|
.data_out(b_reg), .wr_sfr(wr_sfr));
|
|
|
//
|
//
|
//stack pointer
|
//stack pointer
|
// SP
|
// SP
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| Line 202... |
Line 221... |
|
|
|
|
//
|
//
|
//program status word
|
//program status word
|
// PSW
|
// PSW
|
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),
|
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1),
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.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
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.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .p(p), .cy_in(bit_in),
|
.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
|
.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
|
|
|
//
|
//
|
// ports
|
// ports
|
// P0, P1, P2, P3
|
// P0, P1, P2, P3
|
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
|
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
|
.wr_bit(wr_bit_r), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
|
.wr_bit(wr_bit_r), .wr_addr(adr1), .rmw(rmw),
|
.data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),
|
.p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
|
.p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),
|
.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
|
.p3_in(p3_in));
|
.p0_data(p0_data), .p1_data(p1_data), .p2_data(p2_data), .p3_data(p3_data));
|
|
|
//
|
//
|
// serial interface
|
// serial interface
|
// SCON, SBUF
|
// SCON, SBUF
|
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),
|
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in),
|
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
|
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
|
.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(uart_int),
|
.rxd(rxd), .txd(txd), .intr(uart_int),
|
.rclk(rclk), .tclk(tclk), .brate2(brate2),
|
.rclk(rclk), .tclk(tclk), .brate2(brate2),
|
.t1_ow(tf1), .pres_ow(pres_ow));
|
.t1_ow(tf1), .pres_ow(pres_ow),
|
|
.scon(scon), .pcon(pcon), .sbuf(sbuf));
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|
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//
|
//
|
// interrupt control
|
// interrupt control
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// IP, IE, TCON
|
// IP, IE, TCON
|
oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),
|
oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .bit_in(bit_in),
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.ack(int_ack), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
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.ack(int_ack), .data_in(dat1),
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.wr(we), .wr_bit(wr_bit_r),
|
.wr(we), .wr_bit(wr_bit_r),
|
.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
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.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
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.ie0(int0), .ie1(int1),
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.ie0(int0), .ie1(int1),
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.uart_int(uart_int),
|
.uart_int(uart_int),
|
.reti(reti), .intr(intr), .int_vec(int_src));
|
.reti(reti), .intr(intr), .int_vec(int_src),
|
|
.ie(ie), .tcon(tcon), .ip(ip));
|
|
|
|
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//
|
//
|
// timer/counter control
|
// timer/counter control
|
// TH0, TH1, TL0, TH1, TMOD
|
// TH0, TH1, TL0, TH1, TMOD
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oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
|
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1),
|
.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
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.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
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.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow));
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.tr1(tr1), .t0(t0), .t1(t1), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow),
|
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.tmod(tmod), .tl0(tl0), .th0(th0), .tl1(tl1), .th1(th1));
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|
|
//
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//
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// timer/counter 2
|
// timer/counter 2
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// TH2, TH2, RCAPL2L, RCAPL2H, T2CON
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// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
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oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0_r), .data_in(dat1), .wr(we),
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oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1), .wr(we),
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.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex), .data_out(tc2), .bit_out(tc2_bit),
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.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex),
|
.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow));
|
.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow),
|
|
.t2con(t2con), .tl2(tl2), .th2(th2), .rcap2l(rcap2l), .rcap2h(rcap2h));
|
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
| Line 265... |
Line 288... |
wr_bit_r <= #1 wr_bit;
|
wr_bit_r <= #1 wr_bit;
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end
|
end
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|
|
//
|
//
|
//set output in case of address (byte)
|
//set output in case of address (byte)
|
always @(adr0_r or psw or acc or dptr_hi or ports or sp_out or b_reg or uart or
|
always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or
|
tc_out or tc2 or int_out or dptr_lo)
|
//ports
|
|
p0_data or p1_data or p2_data or p3_data or
|
|
//interrupt control
|
|
ie or tcon or ip or
|
|
// t/c 2
|
|
t2con or tl2 or th2 or rcap2l or rcap2h or
|
|
// t/c 0,1
|
|
tmod or tl0 or th0 or tl1 or th1 or
|
|
// serial interface
|
|
scon or pcon or sbuf or
|
|
// stack
|
|
sp_out)
|
begin
|
begin
|
case (adr0_r)
|
case (adr0_r)
|
`OC8051_SFR_ACC: dat0 = acc;
|
`OC8051_SFR_ACC: dat0 = acc;
|
`OC8051_SFR_PSW: dat0 = psw;
|
`OC8051_SFR_PSW: dat0 = psw;
|
`OC8051_SFR_P0: dat0 = ports;
|
`OC8051_SFR_P0: dat0 = p0_data;
|
`OC8051_SFR_P1: dat0 = ports;
|
`OC8051_SFR_P1: dat0 = p1_data;
|
`OC8051_SFR_P2: dat0 = ports;
|
`OC8051_SFR_P2: dat0 = p2_data;
|
`OC8051_SFR_P3: dat0 = ports;
|
`OC8051_SFR_P3: dat0 = p3_data;
|
`OC8051_SFR_SP: dat0 = sp_out;
|
`OC8051_SFR_SP: dat0 = sp_out;
|
`OC8051_SFR_B: dat0 = b_reg;
|
`OC8051_SFR_B: dat0 = b_reg;
|
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
|
`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
|
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
|
`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
|
`OC8051_SFR_SCON: dat0 = uart;
|
`OC8051_SFR_SCON: dat0 = scon;
|
`OC8051_SFR_SBUF: dat0 = uart;
|
`OC8051_SFR_SBUF: dat0 = sbuf;
|
`OC8051_SFR_PCON: dat0 = uart;
|
`OC8051_SFR_PCON: dat0 = pcon;
|
`OC8051_SFR_TH0: dat0 = tc_out;
|
`OC8051_SFR_TH0: dat0 = th0;
|
`OC8051_SFR_TH1: dat0 = tc_out;
|
`OC8051_SFR_TH1: dat0 = th1;
|
`OC8051_SFR_TL0: dat0 = tc_out;
|
`OC8051_SFR_TL0: dat0 = tl0;
|
`OC8051_SFR_TL1: dat0 = tc_out;
|
`OC8051_SFR_TL1: dat0 = tl1;
|
`OC8051_SFR_TMOD: dat0 = tc_out;
|
`OC8051_SFR_TMOD: dat0 = tmod;
|
`OC8051_SFR_IP: dat0 = int_out;
|
`OC8051_SFR_IP: dat0 = ip;
|
`OC8051_SFR_IE: dat0 = int_out;
|
`OC8051_SFR_IE: dat0 = ie;
|
`OC8051_SFR_TCON: dat0 = int_out;
|
`OC8051_SFR_TCON: dat0 = tcon;
|
`OC8051_SFR_RCAP2H: dat0 = tc2;
|
`OC8051_SFR_RCAP2H: dat0 = rcap2h;
|
`OC8051_SFR_RCAP2L: dat0 = tc2;
|
`OC8051_SFR_RCAP2L: dat0 = rcap2l;
|
`OC8051_SFR_TH2: dat0 = tc2;
|
`OC8051_SFR_TH2: dat0 = th2;
|
`OC8051_SFR_TL2: dat0 = tc2;
|
`OC8051_SFR_TL2: dat0 = tl2;
|
`OC8051_SFR_T2CON: dat0 = tc2;
|
`OC8051_SFR_T2CON: dat0 = t2con;
|
default: dat0 = 8'h00;
|
default: dat0 = 8'h00;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
//
|
//
|
//set output in case of address (bit)
|
//set output in case of address (bit)
|
always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit or tc2_bit)
|
always @(adr0_r or psw or acc or b_reg or
|
|
//ports
|
|
p0_data or p1_data or p2_data or p3_data or
|
|
//interrupt control
|
|
ie or tcon or ip or
|
|
// t/c 2
|
|
t2con or
|
|
// serial interface
|
|
scon)
|
begin
|
begin
|
case (adr0_r[7:3])
|
case (adr0_r[7:3])
|
`OC8051_SFR_B_ACC: bit_out = acc_bit;
|
`OC8051_SFR_B_ACC: bit_out = acc[adr0_r[2:0]];
|
`OC8051_SFR_B_PSW: bit_out = psw_bit;
|
`OC8051_SFR_B_PSW: bit_out = psw[adr0_r[2:0]];
|
`OC8051_SFR_B_P0: bit_out = port_bit;
|
`OC8051_SFR_B_P0: bit_out = p0_data[adr0_r[2:0]];
|
`OC8051_SFR_B_P1: bit_out = port_bit;
|
`OC8051_SFR_B_P1: bit_out = p1_data[adr0_r[2:0]];
|
`OC8051_SFR_B_P2: bit_out = port_bit;
|
`OC8051_SFR_B_P2: bit_out = p2_data[adr0_r[2:0]];
|
`OC8051_SFR_B_P3: bit_out = port_bit;
|
`OC8051_SFR_B_P3: bit_out = p3_data[adr0_r[2:0]];
|
`OC8051_SFR_B_B: bit_out = b_bit;
|
`OC8051_SFR_B_B: bit_out = b_reg[adr0_r[2:0]];
|
`OC8051_SFR_B_IP: bit_out = int_bit;
|
`OC8051_SFR_B_IP: bit_out = ip[adr0_r[2:0]];
|
`OC8051_SFR_B_IE: bit_out = int_bit;
|
`OC8051_SFR_B_IE: bit_out = ie[adr0_r[2:0]];
|
`OC8051_SFR_B_TCON: bit_out = int_bit;
|
`OC8051_SFR_B_TCON: bit_out = tcon[adr0_r[2:0]];
|
`OC8051_SFR_B_SCON: bit_out = uart_bit;
|
`OC8051_SFR_B_SCON: bit_out = scon[adr0_r[2:0]];
|
`OC8051_SFR_B_T2CON: bit_out = tc2_bit;
|
`OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
|
default: bit_out = 1'b0;
|
default: bit_out = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
