| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.14 2003/05/07 12:39:20 simont
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// fix bug in case of sequence of inc dptr instrucitons.
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//
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// Revision 1.13 2003/05/05 15:46:37 simont
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// Revision 1.13 2003/05/05 15:46:37 simont
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// add aditional alu destination to solve critical path.
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// add aditional alu destination to solve critical path.
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//
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//
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// Revision 1.12 2003/04/29 11:24:31 simont
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// Revision 1.12 2003/04/29 11:24:31 simont
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// fix bug in case execution of two data dependent instructions.
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// fix bug in case execution of two data dependent instructions.
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| Line 585... |
Line 588... |
((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) //write to dph
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) & !wait_data) begin
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) & !wait_data) begin
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wait_data <= #1 1'b1;
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wait_data <= #1 1'b1;
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end else begin
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end else begin
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case (adr0)
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case (adr0) /* synopsys full_case parallel_case */
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`OC8051_SFR_ACC: dat0 <= #1 acc;
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`OC8051_SFR_ACC: dat0 <= #1 acc;
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`OC8051_SFR_PSW: dat0 <= #1 psw;
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`OC8051_SFR_PSW: dat0 <= #1 psw;
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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| Line 638... |
Line 641... |
`OC8051_SFR_TH2: dat0 <= #1 th2;
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`OC8051_SFR_TH2: dat0 <= #1 th2;
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`OC8051_SFR_TL2: dat0 <= #1 tl2;
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`OC8051_SFR_TL2: dat0 <= #1 tl2;
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`OC8051_SFR_T2CON: dat0 <= #1 t2con;
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`OC8051_SFR_T2CON: dat0 <= #1 t2con;
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`endif
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`endif
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default: dat0 <= #1 8'h00;
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// default: dat0 <= #1 8'h00;
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endcase
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endcase
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wait_data <= #1 1'b0;
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wait_data <= #1 1'b0;
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end
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end
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end
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end
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| Line 661... |
Line 664... |
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bit_out <= #1 dat1[adr0[2:0]];
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bit_out <= #1 dat1[adr0[2:0]];
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else if ((adr1==adr0) & we & wr_bit_r)
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else if ((adr1==adr0) & we & wr_bit_r)
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bit_out <= #1 bit_in;
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bit_out <= #1 bit_in;
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else
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else
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case (adr0[7:3])
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case (adr0[7:3]) /* synopsys full_case parallel_case */
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`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
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`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
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`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
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`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORTS
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`ifdef OC8051_PORT0
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`ifdef OC8051_PORT0
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| Line 696... |
Line 699... |
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`ifdef OC8051_TC2
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`ifdef OC8051_TC2
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`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
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`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
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`endif
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`endif
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default: bit_out <= #1 1'b0;
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// default: bit_out <= #1 1'b0;
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endcase
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endcase
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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