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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 2 and 4

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Rev 2	Rev 4
Line 100...	Line 100...
`if (tl0 == 8'b1111_1111) begin`	`if (tl0 == 8'b1111_1111) begin`
`tf0 <=#1 1'b1;`	`tf0 <=#1 1'b1;`
`tl0 <=#1 th0;`	`tl0 <=#1 th0;`
`end`	`end`
`else begin`	`else begin`
`tl0 <=#1 tl0 + 1;`	`tl0 <=#1 tl0 + 8'h1;`
`tf0 <= #1 1'b0;`	`tf0 <= #1 1'b0;`
`end`	`end`
`end`	`end`
`end`	`end`
`OC8051_MODE3: begin // mode 3	`OC8051_MODE3: begin // mode 3
Line 155...	Line 155...
`if (tl1 == 8'b1111_1111) begin`	`if (tl1 == 8'b1111_1111) begin`
`tf1_1 <=#1 1'b1;`	`tf1_1 <=#1 1'b1;`
`tl1 <=#1 th1;`	`tl1 <=#1 th1;`
`end`	`end`
`else begin`	`else begin`
`tl1 <=#1 tl1 + 1;`	`tl1 <=#1 tl1 + 8'h1;`
`tf1_1 <= #1 1'b0;`	`tf1_1 <= #1 1'b0;`
`end`	`end`
`end`	`end`
`end`	`end`
`default:begin`	`default:begin`
Line 167...	Line 167...
`end`	`end`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

`always @(posedge clk)`	`always @(posedge clk or posedge rst)`
`begin`	`begin`
if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) \|	`if (rst) data_out <= #1 8'h0;`
	else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) \|
(wr_addr==`OC8051_SFR_TH1)\|(wr_addr==`OC8051_SFR_TL0)\|(wr_addr==`OC8051_SFR_TL1)\|	(wr_addr==`OC8051_SFR_TH1)\|(wr_addr==`OC8051_SFR_TL0)\|(wr_addr==`OC8051_SFR_TL1)\|
(wr_addr==`OC8051_SFR_TMOD))) begin	(wr_addr==`OC8051_SFR_TMOD))) begin
`data_out <= #1 data_in;`	`data_out <= #1 data_in;`
`end else begin`	`end else begin`
`case (rd_addr)`	`case (rd_addr)`
Line 185...	Line 186...
`endcase`	`endcase`
`end`	`end`
`end`	`end`


`always @(posedge clk)`	`always @(posedge clk or posedge rst)`
	`if (rst) begin`
	`t0_buff <= #1 1'b0;`
	`t1_buff <= #1 1'b0;`
	`end else begin`
`t0_buff <= #1 t0;`	`t0_buff <= #1 t0;`

`always @(posedge clk)`
`t1_buff <= #1 t1;`	`t1_buff <= #1 t1;`
	`end`
`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Diff between revs 2 and 4