| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2003/06/17 14:17:22 simont
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// BIST signals added.
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//
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// Revision 1.30 2003/06/03 16:51:24 simont
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// Revision 1.30 2003/06/03 16:51:24 simont
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// include "8051_defines" added.
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// include "8051_defines" added.
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//
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//
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// Revision 1.29 2003/05/07 12:36:03 simont
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// Revision 1.29 2003/05/07 12:36:03 simont
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// chsnge comp.des to des1
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// chsnge comp.des to des1
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| Line 253... |
Line 256... |
input scanb_rst;
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input scanb_rst;
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input scanb_clk;
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input scanb_clk;
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input scanb_si;
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input scanb_si;
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output scanb_so;
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output scanb_so;
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input scanb_en;
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input scanb_en;
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wire scanb_soi;
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`endif
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`endif
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wire [7:0] dptr_hi,
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wire [7:0] dptr_hi,
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dptr_lo,
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dptr_lo,
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ri,
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ri,
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| Line 420... |
Line 424... |
.bit_data_out(bit_data)
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.bit_data_out(bit_data)
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`ifdef OC8051_BIST
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`ifdef OC8051_BIST
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,
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,
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.scanb_rst(scanb_rst),
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.scanb_rst(scanb_rst),
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.scanb_clk(scanb_clk),
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.scanb_clk(scanb_clk),
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.scanb_si(scanb_si),
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.scanb_si(scanb_soi),
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.scanb_so(scanb_so),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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.scanb_en(scanb_en)
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`endif
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`endif
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);
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);
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| Line 680... |
Line 684... |
// pins
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// pins
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.dat_i(wbi_dat_i),
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.dat_i(wbi_dat_i),
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.stb_o(wbi_stb_o),
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.stb_o(wbi_stb_o),
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.adr_o(wbi_adr_o),
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.adr_o(wbi_adr_o),
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.ack_i(wbi_ack_i),
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.ack_i(wbi_ack_i),
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.cyc_o(wbi_cyc_o));
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.cyc_o(wbi_cyc_o)
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`ifdef OC8051_BIST
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,
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.scanb_rst(scanb_rst),
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.scanb_clk(scanb_clk),
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.scanb_si(scanb_si),
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.scanb_so(scanb_soi),
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.scanb_en(scanb_en)
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`endif
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);
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
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defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
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defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
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defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
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`ifdef OC8051_SIMULATION
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initial
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$display(" Instruction cache enabled");
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`endif
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//
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//
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// no cache
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// no cache
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//
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//
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`else
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`else
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|
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`ifdef OC8051_BIST
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assign scanb_soi=scanb_si;
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`endif
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`ifdef OC8051_WB
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`ifdef OC8051_WB
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|
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oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
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oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
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// cpu
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// cpu
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.adr_i(iadr_o),
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.adr_i(iadr_o),
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| Line 708... |
Line 735... |
.stb_o(wbi_stb_o),
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.stb_o(wbi_stb_o),
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.adr_o(wbi_adr_o),
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.adr_o(wbi_adr_o),
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.ack_i(wbi_ack_i),
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.ack_i(wbi_ack_i),
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.cyc_o(wbi_cyc_o));
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.cyc_o(wbi_cyc_o));
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|
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`ifdef OC8051_SIMULATION
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initial
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$display(" Wishbone instruction interface enabled");
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`endif
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`else
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`else
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assign wbi_adr_o = iadr_o ;
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assign wbi_adr_o = iadr_o ;
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assign idat_i = wbi_dat_i ;
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assign idat_i = wbi_dat_i ;
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assign wbi_stb_o = 1'b1 ;
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assign wbi_stb_o = 1'b1 ;
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assign iack_i = wbi_ack_i ;
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assign iack_i = wbi_ack_i ;
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assign wbi_cyc_o = 1'b1 ;
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assign wbi_cyc_o = 1'b1 ;
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`ifdef OC8051_SIMULATION
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initial
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$display(" Pipelined instruction interface enabled");
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`endif
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`endif
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`endif
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`endif
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`endif
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