OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Diff between revs 8 and 10

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 8 Rev 10
Line 239... Line 239...
            re_count <= #1 re_count + 4'd1;
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
        end else begin
          if (sam_cnt==3'b011) begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
            if (re_count == 4'd9)
            if (re_count == 4'd9)
            begin
            begin
Line 272... Line 272...
    re_count <= #1 re_count + 4'd1;
    re_count <= #1 re_count + 4'd1;
        end else begin
        end else begin
          r_int <= #1 1'b0;
          r_int <= #1 1'b0;
 
 
          if (sam_cnt==3'b011) begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          end else begin
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sample[sam_cnt[1:0]] <= #1 rxd;
Line 304... Line 304...
            smod_cnt_r <= #1 1'b0;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
        end else begin
          r_int <= #1 1'b0;
          r_int <= #1 1'b0;
          if (sam_cnt==3'b011)
          if (sam_cnt==3'b011)
            if ((sample[0] % sample[1]) | (sample[0] % sample[2]))
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          else begin
          else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sample[sam_cnt[1:0]] <= #1 rxd;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.