URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [branches/] [mkfiles_rev1/] [rtl/] [System09_Xess_XSA-3S1000/] [XSA-3S1000.ucf] - Diff between revs 26 and 28

Rev 26	Rev 28
Line 37...	Line 37...
`NET VGA_VSYNC_N LOC=D8 \| IOSTANDARD = LVCMOS33 ;`	`NET VGA_VSYNC_N LOC=D8 \| IOSTANDARD = LVCMOS33 ;`
`#`	`#`
`# Manually assign locations for the DCMs along the bottom of the FPGA`	`# Manually assign locations for the DCMs along the bottom of the FPGA`
`# because PAR sometimes places them in opposing corners and that ruins the clocks.`	`# because PAR sometimes places them in opposing corners and that ruins the clocks.`
`#`	`#`
`INST "u1/dllint" LOC="DCM_X0Y0";`	`INST "u1/gen_dlls.dllint" LOC="DCM_X0Y0";`
`INST "u1/dllext" LOC="DCM_X1Y0";`	`INST "u1/gen_dlls.dllext" LOC="DCM_X1Y0";`

`# Manually assign locations for the DCMs along the bottom of the FPGA`	`# Manually assign locations for the DCMs along the bottom of the FPGA`
`# because PAR sometimes places them in opposing corners and that ruins the clocks.`	`# because PAR sometimes places them in opposing corners and that ruins the clocks.`
`#INST "u2_dllint" LOC="DCM_X0Y0";`	`#INST "u2_dllint" LOC="DCM_X0Y0";`
`#INST "u2_dllext" LOC="DCM_X1Y0";`	`#INST "u2_dllext" LOC="DCM_X1Y0";`