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//
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//
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// bio.v -- board specific I/O
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// bio.v -- board specific I/O
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//
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//
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module bio(clk, reset,
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`timescale 1ns/10ps
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en, wr, addr,
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`default_nettype none
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module bio(clk, rst,
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stb, we, addr,
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data_in, data_out,
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data_in, data_out,
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wt, spi_en,
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ack, spi_en,
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sw, led,
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sw, led,
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lcd_e, lcd_rw, lcd_rs,
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lcd_e, lcd_rw, lcd_rs,
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spi_ss_b, fpga_init_b);
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spi_ss_b, fpga_init_b);
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// internal interface
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// internal interface
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input clk;
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input clk;
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input reset;
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input rst;
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input en;
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input stb;
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input wr;
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input we;
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input addr;
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input addr;
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input [31:0] data_in;
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input [31:0] data_in;
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output [31:0] data_out;
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output [31:0] data_out;
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output wt;
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output ack;
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output spi_en;
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output spi_en;
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// external interface
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// external interface
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input [3:0] sw;
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input [3:0] sw;
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output [7:0] led;
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output [7:0] led;
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output lcd_e;
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output lcd_e;
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reg [3:0] sw_p;
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reg [3:0] sw_p;
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reg [3:0] sw_s;
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reg [3:0] sw_s;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (rst) begin
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bio_out[31:0] <= 32'h0;
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bio_out[31:0] <= 32'h0;
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end else begin
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end else begin
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if (en & wr & ~addr) begin
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if (stb & we & ~addr) begin
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bio_out[31:0] <= data_in[31:0];
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bio_out[31:0] <= data_in[31:0];
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end
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end
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end
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end
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end
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end
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assign data_out[31:0] =
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assign data_out[31:0] =
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(addr == 0) ? bio_out[31:0] : bio_in[31:0];
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(addr == 0) ? bio_out[31:0] : bio_in[31:0];
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assign wt = 0;
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assign ack = stb;
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assign spi_en = bio_out[31];
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assign spi_en = bio_out[31];
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always @(posedge clk) begin
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always @(posedge clk) begin
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sw_p[3:0] <= sw[3:0];
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sw_p[3:0] <= sw[3:0];
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sw_s[3:0] <= sw_p[3:0];
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sw_s[3:0] <= sw_p[3:0];
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