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[/] [eco32/] [trunk/] [fpga/] [mc/] [src/] [ram/] [ddr/] [ram.v] - Diff between revs 290 and 291

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Rev 290 Rev 291
Line 44... Line 44...
    output sdram_ldm;
    output sdram_ldm;
    inout sdram_udqs;
    inout sdram_udqs;
    inout sdram_ldqs;
    inout sdram_ldqs;
    inout [15:0] sdram_dq;
    inout [15:0] sdram_dq;
 
 
 
  //----------------------------------------------------
 
 
 
  // This is a hack. The synthesizer detected setup timing
 
  // violations on wDAT_I that resulted from crossing the
 
  // 50 MHz to 100 MHz clock domain border. The circuit would
 
  // have functioned perfectly ok, because the signals are
 
  // used only on the following 100 MHz clock edge, a fact
 
  // that the synthesizer was unable to deduce. Instead of
 
  // tolerating formal errors during synthesis, I tried to
 
  // insert a register that is clocked with the trailing
 
  // edge of the 50 MHz clock. Surprisingly, this worked.
 
 
 
  reg [31:0] data_in_buf;
 
 
 
  always @(negedge clk) begin
 
    data_in_buf[31:0] <= data_in[31:0];
 
  end
 
 
 
  //----------------------------------------------------
 
 
  ddr_sdram ddr_sdram_1(
  ddr_sdram ddr_sdram_1(
    .sd_CK_P(sdram_ck_p),
    .sd_CK_P(sdram_ck_p),
    .sd_CK_N(sdram_ck_n),
    .sd_CK_N(sdram_ck_n),
    .sd_A_O(sdram_a[12:0]),
    .sd_A_O(sdram_a[12:0]),
    .sd_BA_O(sdram_ba[1:0]),
    .sd_BA_O(sdram_ba[1:0]),
Line 68... Line 88...
    .reset(~ddr_clk_ok),
    .reset(~ddr_clk_ok),
    .wADR_I(addr[25:2]),
    .wADR_I(addr[25:2]),
    .wSTB_I(stb),
    .wSTB_I(stb),
    .wWE_I(we),
    .wWE_I(we),
    .wWRB_I(4'b1111),
    .wWRB_I(4'b1111),
    .wDAT_I(data_in[31:0]),
    .wDAT_I(data_in_buf[31:0]),
    .wDAT_O(data_out[31:0]),
    .wDAT_O(data_out[31:0]),
    .wACK_O(ack)
    .wACK_O(ack)
  );
  );
 
 
endmodule
endmodule

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