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Line 24... |
#include "svdpi.h"
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#include "svdpi.h"
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#include "../dpiheader.h"
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#include "../dpiheader.h"
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// define RTC address values
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// define RTC address values
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#define RTC_CTRL 0x00000000
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#define RTC_CTRL 0x00000000
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#define RTC_NULL_0x4 0x00000004
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#define RTC_NULL_0x04 0x00000004
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#define RTC_NULL_0x8 0x00000008
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#define RTC_NULL_0x08 0x00000008
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#define RTC_NULL_0xC 0x0000000C
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#define RTC_NULL_0x0C 0x0000000C
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#define RTC_TIME_SEC_H 0x00000010
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#define RTC_TIME_SEC_H 0x00000010
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#define RTC_TIME_SEC_L 0x00000014
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#define RTC_TIME_SEC_L 0x00000014
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#define RTC_TIME_NSC_H 0x00000018
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#define RTC_TIME_NSC_H 0x00000018
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#define RTC_TIME_NSC_L 0x0000001C
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#define RTC_TIME_NSC_L 0x0000001C
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#define RTC_PERIOD_H 0x00000020
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#define RTC_PERIOD_H 0x00000020
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// define RTC constant
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// define RTC constant
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#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
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#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
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#define RTC_ACCMOD_L 0x0 // 256 for 8bit
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#define RTC_ACCMOD_L 0x0 // 256 for 8bit
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// define TSU address values
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// define TSU address values
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#define TSU_CTRL 0x00000040
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#define TSU_RXCTRL 0x00000040
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#define TSU_RXQUE_STATUS 0x00000044
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#define TSU_RXQUE_STATUS 0x00000044
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#define TSU_TXQUE_STATUS 0x00000048
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#define TSU_NULL_0x48 0x00000048
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#define TSU_NULL_0x4C 0x0000004C
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#define TSU_NULL_0x4C 0x0000004C
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#define TSU_NULL_0x50 0x00000050
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#define TSU_RXQUE_DATA_HH 0x00000050
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#define TSU_NULL_0x54 0x00000054
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#define TSU_RXQUE_DATA_HL 0x00000054
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#define TSU_NULL_0x58 0x00000058
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#define TSU_RXQUE_DATA_LH 0x00000058
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#define TSU_NULL_0x5C 0x0000005C
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#define TSU_RXQUE_DATA_LL 0x0000005C
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#define TSU_RXQUE_DATA_HH 0x00000060
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#define TSU_TXCTRL 0x00000060
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#define TSU_RXQUE_DATA_HL 0x00000064
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#define TSU_TXQUE_STATUS 0x00000064
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#define TSU_RXQUE_DATA_LH 0x00000068
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#define TSU_NULL_0x68 0x00000068
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#define TSU_RXQUE_DATA_LL 0x0000006C
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#define TSU_NULL_0x6C 0x0000006C
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#define TSU_TXQUE_DATA_HH 0x00000070
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#define TSU_TXQUE_DATA_HH 0x00000070
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#define TSU_TXQUE_DATA_HL 0x00000074
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#define TSU_TXQUE_DATA_HL 0x00000074
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#define TSU_TXQUE_DATA_LH 0x00000078
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#define TSU_TXQUE_DATA_LH 0x00000078
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#define TSU_TXQUE_DATA_LL 0x0000007C
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#define TSU_TXQUE_DATA_LL 0x0000007C
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// define TSU control values
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// define TSU control values
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#define TSU_SET_CTRL_0 0x00
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#define TSU_SET_CTRL_0 0x00
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#define TSU_GET_RXQUE 0x01
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#define TSU_SET_RXRST 0x02
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#define TSU_GET_TXQUE 0x01
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#define TSU_GET_TXQUE 0x01
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#define TSU_SET_TXRST 0x02
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#define TSU_SET_TXRST 0x02
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#define TSU_GET_RXQUE 0x04
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#define TSU_SET_RXRST 0x08
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int ptp_drv_bfm_c(double fw_delay)
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int ptp_drv_bfm_c(double fw_delay)
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{
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{
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unsigned int cpu_addr_i;
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unsigned int cpu_addr_i;
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unsigned int cpu_data_i;
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unsigned int cpu_data_i;
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Line 228... |
int i;
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int i;
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int rx_queue_num;
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int rx_queue_num;
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int tx_queue_num;
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int tx_queue_num;
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// RESET TSU
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// RESET TSU
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_RXCTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_RXCTRL;
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cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;
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cpu_data_i = TSU_SET_RXRST;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_TXCTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_TXCTRL;
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cpu_data_i = TSU_SET_TXRST;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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// READ TSU
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// READ TSU
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while (1) {
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while (1) {
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Line 257... |
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if (rx_queue_num > 0x0) {
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if (rx_queue_num > 0x0) {
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for (i=rx_queue_num; i>0; i--) {
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for (i=rx_queue_num; i>0; i--) {
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// READ TSU RX FIFO
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// READ TSU RX FIFO
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_RXCTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_RXCTRL;
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cpu_data_i = TSU_GET_RXQUE;
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cpu_data_i = TSU_GET_RXQUE;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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do {
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do {
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_RXCTRL;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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//printf("%08x\n", cpu_data_o);
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//printf("%08x\n", cpu_data_o);
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} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
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} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
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cpu_addr_i = TSU_RXQUE_DATA_HH;
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cpu_addr_i = TSU_RXQUE_DATA_HH;
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Line 330... |
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if (tx_queue_num > 0x0) {
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if (tx_queue_num > 0x0) {
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for (i=tx_queue_num; i>0; i--) {
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for (i=tx_queue_num; i>0; i--) {
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// READ TSU TX FIFO
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// READ TSU TX FIFO
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_TXCTRL;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_data_i = TSU_SET_CTRL_0;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_TXCTRL;
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cpu_data_i = TSU_GET_TXQUE;
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cpu_data_i = TSU_GET_TXQUE;
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cpu_wr(cpu_addr_i, cpu_data_i);
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cpu_wr(cpu_addr_i, cpu_data_i);
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do {
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do {
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cpu_addr_i = TSU_CTRL;
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cpu_addr_i = TSU_TXCTRL;
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cpu_rd(cpu_addr_i, &cpu_data_o);
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cpu_rd(cpu_addr_i, &cpu_data_o);
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//printf("%08x\n", cpu_data_o);
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//printf("%08x\n", cpu_data_o);
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} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
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} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
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cpu_addr_i = TSU_TXQUE_DATA_HH;
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cpu_addr_i = TSU_TXQUE_DATA_HH;
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