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--##############################################################################
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--##############################################################################
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-- light8080 : Intel 8080 binary compatible core
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-- light8080 : Intel 8080 binary compatible core
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--##############################################################################
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--##############################################################################
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-- v1.2 (08 jul 2010) Fix: XOR operations were not clearing CY,ACY.
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- v1.1 (20 sep 2008) Microcode bug in INR fixed.
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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-- v1.0 (05 nov 2007) First release. Jose A. Ruiz.
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--
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--
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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-- This file and all the light8080 project files are freeware (See COPYING.TXT)
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--##############################################################################
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--##############################################################################
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signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
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signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.)
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signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
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signal do_cy_op_d : std_logic; -- do_cy_op, pipelined
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signal do_cpc : std_logic; -- ALU operation is CPC
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signal do_cpc : std_logic; -- ALU operation is CPC
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signal do_cpc_d : std_logic; -- do_cpc, pipelined
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signal do_cpc_d : std_logic; -- do_cpc, pipelined
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signal do_daa : std_logic; -- ALU operation is DAA
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signal do_daa : std_logic; -- ALU operation is DAA
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signal do_xor : std_logic; -- ALU operation is some XOR (clears CY)
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signal flag_ac : std_logic; -- new computed half carry flag
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signal flag_ac : std_logic; -- new computed half carry flag
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-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
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-- flag_aux_cy: new computed half carry flag (used in 16-bit ops)
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signal flag_aux_cy : std_logic;
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signal flag_aux_cy : std_logic;
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signal load_psw : std_logic; -- load F register
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signal load_psw : std_logic; -- load F register
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flag_pattern <= ucode_field2(9 downto 8);
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flag_pattern <= ucode_field2(9 downto 8);
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use_aux_cy <= ucode_field2(19);
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use_aux_cy <= ucode_field2(19);
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do_cpc <= ucode_field2(23);
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do_cpc <= ucode_field2(23);
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do_cy_op <= ucode_field2(24);
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do_cy_op <= ucode_field2(24);
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do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
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do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0';
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do_xor <= '1' when ucode_field2(5 downto 0) = "000101" else '0';
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aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
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aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1';
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-- carry input selection: normal or aux (for 16 bit increments)?
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-- carry input selection: normal or aux (for 16 bit increments)?
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cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
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cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in;
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flag_s <= alu_output(7);
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flag_s <= alu_output(7);
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flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
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flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor
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alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
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alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0));
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flag_z <= '1' when alu_output=X"00" else '0';
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flag_z <= '1' when alu_output=X"00" else '0';
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flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
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-- FIXED 08/JUL/2010: XOR was not clearing AC as it should
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--flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4));
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flag_cy_1 <= cy_arith when use_logic = '1' else cy_shifter;
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flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4)) and not do_xor;
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-- FIXED 08/JUL/2010: XOR was not clearing CY as it should
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--flag_cy_1 <= cy_arith when use_logic = '1' else cy_shifter;
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flag_cy_1 <= '0' when do_xor='1' else
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cy_arith when use_logic = '1' and do_xor='0' else
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cy_shifter;
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flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
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flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc
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flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
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flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2;
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flag_aux_cy <= cy_adder;
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flag_aux_cy <= cy_adder;
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