| Line 1... |
Line 1... |
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Generated from template tb_template.vhdl by hexconv.pl
|
-- Generated from template tb_template.vhdl by hexconv.pl
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Light8080 simulation test bench.
|
-- Light8080 simulation test bench.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Source for the 8080 program is in asm\tb1.asm
|
-- This test bench was built from a generic template. The details on what tests
|
|
-- are performed by this test bench can be found in the assembly source for the
|
|
-- 8080 program, in file asm\tb1.asm.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
--
|
--
|
-- This test bench provides a simulated CPU system to test programs. This test
|
-- This test bench provides a simulated CPU system to test programs. This test
|
-- bench does not do any assertions or checks, all assertions are left to the
|
-- bench does not do any assertions or checks, all assertions are left to the
|
-- software.
|
-- software.
|
| Line 17... |
Line 19... |
-- Besides, it provides some means to trigger hardware irq from software,
|
-- Besides, it provides some means to trigger hardware irq from software,
|
-- including the specification of the instructions fed to the CPU as interrupt
|
-- including the specification of the instructions fed to the CPU as interrupt
|
-- vectors during inta cycles.
|
-- vectors during inta cycles.
|
--
|
--
|
-- We will simulate 8 possible irq sources. The software can trigger any one of
|
-- We will simulate 8 possible irq sources. The software can trigger any one of
|
-- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq
|
-- them by writing at ports 0x010 to 0x011. Port 0x010 holds the irq source to
|
-- source to be triggered (0 to 7) and register 0x011 holds the number of clock
|
-- be triggered (0 to 7) and port 0x011 holds the number of clock cycles that
|
-- cycles that will elapse from the end of the instruction that writes to the
|
-- will elapse from the end of the instruction that writes to the register to
|
-- register to the assertion of intr.
|
-- the assertion of intr. Port 0x012 holds the number of cycles intr will remain
|
|
-- high. Intr will be asserted for 1 cycle at least, so writing a 0 here is the
|
|
-- same as writing 1.
|
--
|
--
|
-- When the interrupt is acknowledged and inta is asserted, the test bench reads
|
-- When the interrupt is acknowledged and inta is asserted, the test bench reads
|
-- the value at register 0x010 as the irq source, and feeds an instruction to
|
-- the value at register 0x010 as the irq source, and feeds an instruction to
|
-- the CPU starting from the RAM address 0040h+source*4.
|
-- the CPU starting from the RAM address 0040h+source*4.
|
-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
|
-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
|
-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
|
-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
|
-- software to easily test different interrupt vectors without any hand
|
-- software to easily test different interrupt vectors without any hand
|
-- assembly. All of this is strictly simulation-only stuff.
|
-- assembly. All of this is strictly simulation-only stuff.
|
--
|
--
|
--
|
|
-- Upon completion, the software must write a value to register 0x020. Writing
|
-- Upon completion, the software must write a value to register 0x020. Writing
|
-- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and
|
-- a 0x055 means 'success', writing a 0x0aa means 'failure'. The write operation
|
-- failure conditions are defined by the software.
|
-- will stop the simulation. Success and failure conditions are defined by the
|
|
-- software.
|
|
--
|
|
-- If a time period defined as constant MAX_SIM_LENGTH passes before anything
|
|
-- is written to io address 0x020, the test bench assumes the software ran away
|
|
-- and quits with an error message.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.ALL;
|
use ieee.std_logic_1164.ALL;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
| Line 53... |
Line 61... |
|
|
-- T: simulated clock period
|
-- T: simulated clock period
|
constant T : time := 100 ns;
|
constant T : time := 100 ns;
|
|
|
-- MAX_SIM_LENGTH: maximum simulation time
|
-- MAX_SIM_LENGTH: maximum simulation time
|
constant MAX_SIM_LENGTH : time := T*5000;
|
constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
-- Component Declaration for the Unit Under Test (UUT)
|
| Line 107... |
Line 115... |
|
|
X"c3",X"60",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"c3",X"60",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"c6",X"07",X"fb",X"c9",X"00",X"00",X"00",X"00",
|
X"c6",X"01",X"fb",X"c9",X"00",X"00",X"00",X"00",
|
X"47",X"c9",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"3c",X"fb",X"c9",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"3c",X"00",X"00",X"00",X"cf",X"00",X"00",X"00",
|
X"3c",X"00",X"00",X"00",X"ef",X"00",X"00",X"00",
|
X"23",X"00",X"00",X"00",X"3e",X"42",X"00",X"00",
|
X"23",X"00",X"00",X"00",X"3e",X"42",X"00",X"00",
|
X"21",X"34",X"12",X"00",X"c3",X"10",X"01",X"00",
|
X"21",X"34",X"12",X"00",X"c3",X"2f",X"01",X"00",
|
X"cd",X"15",X"01",X"00",X"cd",X"18",X"01",X"00",
|
X"cd",X"34",X"01",X"00",X"cd",X"37",X"01",X"00",
|
X"31",X"5b",X"01",X"3e",X"13",X"e7",X"fe",X"1a",
|
X"31",X"7a",X"01",X"3e",X"13",X"e7",X"fe",X"14",
|
X"c2",X"0b",X"01",X"3e",X"00",X"d3",X"10",X"fb",
|
X"c2",X"2a",X"01",X"3e",X"00",X"d3",X"10",X"fb",
|
X"3e",X"14",X"d3",X"11",X"3e",X"27",X"00",X"00",
|
X"3e",X"14",X"d3",X"11",X"3e",X"27",X"00",X"00",
|
X"00",X"00",X"fe",X"28",X"c2",X"0b",X"01",X"3e",
|
X"00",X"00",X"fe",X"28",X"c2",X"2a",X"01",X"3e",
|
X"01",X"d3",X"10",X"fb",X"3e",X"14",X"d3",X"11",
|
X"01",X"d3",X"10",X"fb",X"3e",X"14",X"d3",X"11",
|
X"3e",X"20",X"00",X"00",X"00",X"00",X"fe",X"27",
|
X"3e",X"20",X"00",X"00",X"00",X"00",X"fe",X"21",
|
X"c2",X"0b",X"01",X"21",X"ff",X"13",X"3e",X"02",
|
X"c2",X"2a",X"01",X"21",X"ff",X"13",X"3e",X"02",
|
X"d3",X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",
|
X"d3",X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",
|
X"00",X"7d",X"fe",X"00",X"c2",X"0b",X"01",X"7c",
|
X"00",X"7d",X"fe",X"00",X"c2",X"2a",X"01",X"7c",
|
X"fe",X"14",X"c2",X"0b",X"01",X"3e",X"03",X"d3",
|
X"fe",X"14",X"c2",X"2a",X"01",X"3e",X"03",X"d3",
|
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
|
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
|
X"fe",X"42",X"c2",X"0b",X"01",X"3e",X"04",X"d3",
|
X"fe",X"42",X"c2",X"2a",X"01",X"3e",X"04",X"d3",
|
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
|
X"10",X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",
|
X"7c",X"fe",X"12",X"c2",X"0b",X"01",X"7d",X"fe",
|
X"7c",X"fe",X"12",X"c2",X"2a",X"01",X"7d",X"fe",
|
X"34",X"c2",X"0b",X"01",X"3e",X"05",X"d3",X"10",
|
X"34",X"c2",X"2a",X"01",X"3e",X"05",X"d3",X"10",
|
X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",X"fe",
|
X"fb",X"3e",X"04",X"d3",X"11",X"00",X"00",X"fe",
|
X"79",X"c2",X"0b",X"01",X"3e",X"06",X"d3",X"10",
|
X"79",X"c2",X"2a",X"01",X"3e",X"06",X"d3",X"10",
|
X"fb",X"3e",X"04",X"d3",X"11",X"3c",X"00",X"fe",
|
X"fb",X"3e",X"04",X"d3",X"11",X"3c",X"00",X"fe",
|
X"05",X"c2",X"0b",X"01",X"78",X"fe",X"19",X"c2",
|
X"05",X"c2",X"2a",X"01",X"78",X"fe",X"19",X"c2",
|
X"0b",X"01",X"f3",X"3e",X"07",X"d3",X"10",X"3e",
|
X"2a",X"01",X"f3",X"3e",X"07",X"d3",X"10",X"3e",
|
X"04",X"d3",X"11",X"00",X"00",X"00",X"3e",X"55",
|
X"04",X"d3",X"11",X"00",X"00",X"00",X"3e",X"50",
|
X"d3",X"20",X"76",X"3e",X"aa",X"d3",X"20",X"76",
|
X"d3",X"12",X"3e",X"01",X"d3",X"10",X"fb",X"3e",
|
X"3e",X"79",X"c3",X"df",X"00",X"06",X"19",X"c9",
|
X"14",X"d3",X"11",X"3e",X"27",X"00",X"00",X"3c",
|
X"c3",X"0b",X"01",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"3c",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"fe",X"2c",X"c2",X"2a",X"01",X"3e",X"55",X"d3",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"20",X"76",X"3e",X"aa",X"d3",X"20",X"76",X"3e",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"79",X"c3",X"df",X"00",X"06",X"19",X"c9",X"c3",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"2a",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
| Line 365... |
Line 373... |
);
|
);
|
|
|
signal irq_vector_byte: std_logic_vector(7 downto 0);
|
signal irq_vector_byte: std_logic_vector(7 downto 0);
|
signal irq_source : integer range 0 to 7;
|
signal irq_source : integer range 0 to 7;
|
signal cycles_to_intr : integer range -10 to 255;
|
signal cycles_to_intr : integer range -10 to 255;
|
|
signal intr_width : integer range 0 to 255;
|
signal int_vector_index : integer range 0 to 3;
|
signal int_vector_index : integer range 0 to 3;
|
signal addr_vector_table: integer range 0 to 65535;
|
signal addr_vector_table: integer range 0 to 65535;
|
|
|
begin
|
begin
|
|
|
| Line 445... |
Line 454... |
process(clk)
|
process(clk)
|
begin
|
begin
|
if (clk'event and clk='1') then
|
if (clk'event and clk='1') then
|
if reset='1' then
|
if reset='1' then
|
cycles_to_intr <= -10; -- meaning no interrupt pending
|
cycles_to_intr <= -10; -- meaning no interrupt pending
|
intr_i <= '0';
|
|
else
|
else
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
|
cycles_to_intr <= conv_integer(data_o) + 1;
|
cycles_to_intr <= conv_integer(data_o) + 1;
|
else
|
else
|
if cycles_to_intr >= 0 then
|
if cycles_to_intr >= 0 then
|
cycles_to_intr <= cycles_to_intr - 1;
|
cycles_to_intr <= cycles_to_intr - 1;
|
end if;
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process irq_trigger_register;
|
|
|
|
irq_pulse_width_register:
|
|
process(clk)
|
|
variable intr_pulse_countdown : integer;
|
|
begin
|
|
if (clk'event and clk='1') then
|
|
if reset='1' then
|
|
intr_width <= 1;
|
|
intr_pulse_countdown := 0;
|
|
intr_i <= '0';
|
|
else
|
|
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"12" then
|
|
intr_width <= conv_integer(data_o) + 1;
|
|
end if;
|
|
|
if cycles_to_intr = 0 then
|
if cycles_to_intr = 0 then
|
intr_i <= '1';
|
intr_i <= '1';
|
else
|
intr_pulse_countdown := intr_width;
|
|
elsif intr_pulse_countdown <= 1 then
|
intr_i <= '0';
|
intr_i <= '0';
|
|
else
|
|
intr_pulse_countdown := intr_pulse_countdown - 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process irq_pulse_width_register;
|
end process irq_trigger_register;
|
|
|
|
|
|
irq_source_register:
|
irq_source_register:
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if (clk'event and clk='1') then
|
if (clk'event and clk='1') then
|
