| Line 35... |
Line 35... |
------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 12/20/13 Design Start
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-- Seth Henry 12/20/13 Design Start
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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-- Seth Henry 04/10/20 Code cleanup and register documentation
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-- Also removed "input only" generic, as there is a
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-- Also removed "input only" generic, as there is a
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-- separate module for that
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-- separate module for that
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-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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| Line 46... |
Line 47... |
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entity o8_gpio is
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entity o8_gpio is
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generic(
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generic(
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Default_Out : DATA_TYPE := x"00";
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Default_Out : DATA_TYPE := x"00";
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Default_En : DATA_TYPE := x"00";
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Default_En : DATA_TYPE := x"00";
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Reset_Level : std_logic := '1';
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Clock : in std_logic;
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Reset : in std_logic;
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--
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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--
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--
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GPIO : inout DATA_TYPE
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GPIO : inout DATA_TYPE
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);
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);
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end entity;
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end entity;
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architecture behave of o8_gpio is
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architecture behave of o8_gpio is
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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constant User_Addr : std_logic_vector(15 downto 2)
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constant User_Addr : std_logic_vector(15 downto 2)
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:= Address(15 downto 2);
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:= Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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