URL
https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [busmaster.v] - Diff between revs 30 and 32
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 30 |
Rev 32 |
Line 1189... |
Line 1189... |
wire sdram_trigger;
|
wire sdram_trigger;
|
wire [31:0] sdram_debug;
|
wire [31:0] sdram_debug;
|
assign sdram_trigger = (ram_sel)&&(wb_stb);
|
assign sdram_trigger = (ram_sel)&&(wb_stb);
|
assign sdram_debug= i_ram_dbg;
|
assign sdram_debug= i_ram_dbg;
|
|
|
wbscope #(5'd9,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
|
wbscope #(5'd9,32,1)
|
|
ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
|
i_clk, wb_cyc,
|
|
((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
|
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
|
scop_sdram_interrupt);
|
scop_sdram_interrupt);
|
|
|
assign scop_c_ack = scop_sdram_ack;
|
assign scop_c_ack = scop_sdram_ack;
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.