| Line 108... |
Line 108... |
input i_aux_rx, i_aux_rts;
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input i_aux_rx, i_aux_rts;
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output wire o_aux_tx, o_aux_cts;
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output wire o_aux_tx, o_aux_cts;
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`define FULLCLOCK
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`define FULLCLOCK
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// Build our master clock
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// Build our master clock
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wire i_clk, clk_for_ddr, mem_serial_clk, mem_serial_clk_inv,
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wire s_clk_pll, s_clk, clk_for_ddr, mem_serial_clk, mem_serial_clk_inv,
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enet_clk, clk_halfspeed, clk_feedback, clk_locked, clk_unused;
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enet_clk, clk_halfspeed, clk_feedback, clk_locked, clk_unused;
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PLLE2_BASE #(
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PLLE2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_PHASE(0.0), // Phase off. in deg of CLKFB,(-360-360)
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
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.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
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.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
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`ifdef FULLCLOCK
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE:
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// divide amount for each CLKOUT(1-128)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(4), // 200 MHz
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.CLKOUT1_DIVIDE(1), // 800 MHz clock for DDR memory
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.CLKOUT2_DIVIDE(1), // 800 MHz clock to run DDR I/O
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.CLKOUT3_DIVIDE(1), // 800MHz clk inv to run DDR I/O
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.CLKOUT4_DIVIDE(8), // 100 MHz
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.CLKOUT5_DIVIDE(32), // 25 MHz
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`else
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// 100*64/40 = 160 -- the fastest speed where the UART will
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// still work at 4MBaud. Others will still support 115200
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// Baud
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// 100*64/36 = 177.78
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// 100*64/34 = 188.24
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// 100*64/33 = 193.94
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
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.CLKOUT0_DIVIDE(5), // 160 MHz
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.CLKOUT0_DIVIDE(5), // 160 MHz
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.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
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.CLKOUT1_DIVIDE(10), // 80 MHz (Unused)
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.CLKOUT2_DIVIDE(5), // 160 MHz // Clock too slow for DDR
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.CLKOUT2_DIVIDE(16), // 50 MHz (Unused)
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.CLKOUT3_DIVIDE(5), // 160 MHz // Clock too slow for DDR
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.CLKOUT3_DIVIDE(32), // 25 MHz (Unused/Ethernet clock)
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.CLKOUT4_DIVIDE(20), // 40 MHz
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.CLKOUT4_DIVIDE(16), // 50 MHz (Unused clock?)
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.CLKOUT5_DIVIDE(5),
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.CLKOUT5_DIVIDE(24),
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`endif
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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// CLKOUT0_PHASE -- phase offset for each CLKOUT
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.CLKOUT0_PHASE(0.0),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(270.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(180.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.DIVCLK_DIVIDE(1), // Master division value , (1-56)
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.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
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.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
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.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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) genclock(
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) genclock(
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// Clock outputs: 1-bit (each) output
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// Clock outputs: 1-bit (each) output
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.CLKOUT0(i_clk),
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.CLKOUT0(s_clk_pll),
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.CLKOUT1(clk_for_ddr),
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.CLKOUT1(mem_clk),
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.CLKOUT2(mem_serial_clk),
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.CLKOUT2(clk2_unused),
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.CLKOUT3(mem_serial_clk_inv),
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.CLKOUT3(enet_clk),
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.CLKOUT4(clk_unused),
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.CLKOUT4(clk4_unused),
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.CLKOUT5(enet_clk),
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.CLKOUT5(clk5_unused),
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
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.LOCKED(clk_locked),
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.LOCKED(clk_locked),
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.CLKIN1(i_clk_100mhz),
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.CLKIN1(i_clk_100mhz),
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.PWRDWN(1'b0),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.RST(1'b0),
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.CLKFBIN(clk_feedback) // 1-bit input, feedback clock
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.CLKFBIN(clk_feedback_bufd) // 1-bit input, feedback clock
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);
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);
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// Help reduce skew ...
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BUFG sys_clk_buffer( .I(s_clk_pll), .O(s_clk));
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BUFG feedback_buffer(.I(clk_feedback),.O(clk_feedback_bufd));
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// UART interface
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// UART interface
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wire [29:0] bus_uart_setup;
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wire [29:0] bus_uart_setup;
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`ifdef FULLCLOCK
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assign bus_uart_setup = 30'h10000028; // 4MBaud, 7 bits
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assign bus_uart_setup = 30'h10000032; // 4MBaud, 7 bits
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`else
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assign bus_uart_setup = 30'h10000028;//4MBaud,7 bits,@160MHzClk
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//assign bus_uart_setup = 30'h10000019;//4MBaud,7 bits,@100MHzClk
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`endif
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wire [7:0] rx_data, tx_data;
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wire [7:0] rx_data, tx_data;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
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wire tx_stb, tx_busy;
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wire tx_stb, tx_busy;
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| Line 200... |
Line 182... |
reg pwr_reset, pre_reset;
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reg pwr_reset, pre_reset;
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//
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//
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// Logic description starts with the PRE-reset, so as to make certain
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// Logic description starts with the PRE-reset, so as to make certain
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// we include the reset button
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// we include the reset button
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initial pre_reset = 1'b0;
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initial pre_reset = 1'b0;
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always @(posedge i_clk)
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always @(posedge s_clk)
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pre_reset <= ~i_reset_btn;
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pre_reset <= ~i_reset_btn;
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//
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//
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// and then continues with the actual reset, now that we've
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// and then continues with the actual reset, now that we've
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// synchronized our reset button wire.
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// synchronized our reset button wire.
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge s_clk)
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pwr_reset <= pre_reset;
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pwr_reset <= pre_reset;
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wire w_ck_uart, w_uart_tx;
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wire w_ck_uart, w_uart_tx;
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rxuart rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
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rxuart rcv(s_clk, pwr_reset, bus_uart_setup, i_uart_rx,
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rx_stb, rx_data, rx_break,
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rx_stb, rx_data, rx_break,
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rx_parity_err, rx_frame_err, w_ck_uart);
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rx_parity_err, rx_frame_err, w_ck_uart);
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txuart txv(i_clk, pwr_reset, bus_uart_setup, 1'b0,
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txuart txv(s_clk, pwr_reset, bus_uart_setup, 1'b0,
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tx_stb, tx_data, o_uart_tx, tx_busy);
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tx_stb, tx_data, o_uart_tx, tx_busy);
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| Line 400... |
Line 382... |
wire [1:0] qspi_bmod;
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wire [1:0] qspi_bmod;
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wire [3:0] qspi_dat;
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wire [3:0] qspi_dat;
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wire [3:0] i_qspi_dat;
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wire [3:0] i_qspi_dat;
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//
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//
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wire [2:0] w_ddr_dqs;
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wire [31:0] wo_ddr_data, wi_ddr_data;
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//
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wire w_mdio, w_mdwe;
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wire w_mdio, w_mdwe;
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//
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//
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wire w_sd_cmd;
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wire w_sd_cmd;
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wire [3:0] w_sd_data;
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wire [3:0] w_sd_data;
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fastmaster wbbus(i_clk, pwr_reset,
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fastmaster wbbus(s_clk, pwr_reset,
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// External USB-UART bus control
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// External USB-UART bus control
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rx_stb, rx_data, tx_stb, tx_data, tx_busy,
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rx_stb, rx_data, tx_stb, tx_data, tx_busy,
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// Board lights and switches
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// Board lights and switches
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i_sw, i_btn, o_led,
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i_sw, i_btn, o_led,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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| Line 448... |
Line 433... |
//
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//
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// ?? Dual mode in (not yet)
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// ?? Dual mode in (not yet)
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// ?? Dual mode out (not yet)
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// ?? Dual mode out (not yet)
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//
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//
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//
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//
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// `define QSPI_OUT_VERSION_ONE
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`ifdef QSPI_OUT_VERSION_ONE
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assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
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:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
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assign i_qspi_dat = io_qspi_dat;
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assign o_qspi_sck = w_qspi_sck;
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`else
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wire [3:0] i_qspi_pedge, i_qspi_nedge;
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wire [3:0] i_qspi_pedge, i_qspi_nedge;
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xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
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xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
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xoddr xqspi_csn( i_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
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xoddr xqspi_csn( i_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
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//
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//
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xioddr xqspi_d0( i_clk, (qspi_bmod != 2'b11),
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xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11),
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{ qspi_dat[0], qspi_dat[0] },
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{ qspi_dat[0], qspi_dat[0] },
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{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
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{ i_qspi_pedge[0], i_qspi_nedge[0] }, io_qspi_dat[0]);
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xioddr xqspi_d1( i_clk, (qspi_bmod==2'b10),
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xioddr xqspi_d1( s_clk, (qspi_bmod==2'b10),
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{ qspi_dat[1], qspi_dat[1] },
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{ qspi_dat[1], qspi_dat[1] },
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{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
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{ i_qspi_pedge[1], i_qspi_nedge[1] }, io_qspi_dat[1]);
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xioddr xqspi_d2( i_clk, (qspi_bmod!=2'b11),
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xioddr xqspi_d2( s_clk, (qspi_bmod!=2'b11),
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(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
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(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
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{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
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{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
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xioddr xqspi_d3( i_clk, (qspi_bmod!=2'b11),
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xioddr xqspi_d3( s_clk, (qspi_bmod!=2'b11),
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(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
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(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
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{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
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{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
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|
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assign i_qspi_dat = i_qspi_pedge;
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assign i_qspi_dat = i_qspi_pedge;
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`endif
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//
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// Proposed QSPI mode select, to allow dual I/O mode
|
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// 000 Normal SPI mode
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// 001 Dual mode input
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// 010 Dual mode, output
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// 101 Quad I/O mode input
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// 110 Quad I/O mode output
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//
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//
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//
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//
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//
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//
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// Wires for setting up the SD Card Controller
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// Wires for setting up the SD Card Controller
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//
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//
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