| Line 99... |
Line 99... |
// And, finally, for a final flair --- offer to interrupt the CPU after
|
// And, finally, for a final flair --- offer to interrupt the CPU after
|
// our trigger has gone off. This line is equivalent to the scope
|
// our trigger has gone off. This line is equivalent to the scope
|
// being stopped. It is not maskable here.
|
// being stopped. It is not maskable here.
|
output wire o_interrupt;
|
output wire o_interrupt;
|
|
|
// For timing's sake, let's remove ourselves from the bus a touch
|
|
reg r_wb_stb, r_wb_addr, r_wb_we;
|
|
reg [31:0] r_wb_data;
|
|
always @(posedge i_clk)
|
|
begin
|
|
r_wb_stb <= i_wb_stb;
|
|
r_wb_we <= i_wb_we;
|
|
r_wb_addr<= i_wb_addr;
|
|
r_wb_data<= i_wb_data;
|
|
end
|
|
|
|
reg [(LGMEM-1):0] raddr;
|
reg [(LGMEM-1):0] raddr;
|
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
|
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
|
|
|
// Our status/config register
|
// Our status/config register
|
wire bw_reset_request, bw_manual_trigger,
|
wire bw_reset_request, bw_manual_trigger,
|
bw_disable_trigger, bw_reset_complete;
|
bw_disable_trigger, bw_reset_complete;
|
reg [22:0] br_config;
|
reg [22:0] br_config;
|
wire [19:0] bw_holdoff;
|
wire [19:0] bw_holdoff;
|
initial br_config = ((1<<(LGMEM-1))-4);
|
initial br_config = ((1<<(LGMEM-1))-4);
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if ((r_wb_stb)&&(~r_wb_addr))
|
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
|
begin
|
begin
|
if (r_wb_we)
|
if (i_wb_we)
|
br_config <= { r_wb_data[31],
|
br_config <= { i_wb_data[31],
|
(r_wb_data[27]),
|
(i_wb_data[27]),
|
r_wb_data[26],
|
i_wb_data[26],
|
r_wb_data[19:0] };
|
i_wb_data[19:0] };
|
end else if (bw_reset_complete)
|
end else if (bw_reset_complete)
|
br_config[22] <= 1'b1;
|
br_config[22] <= 1'b1;
|
assign bw_reset_request = (~br_config[22]);
|
assign bw_reset_request = (~br_config[22]);
|
assign bw_manual_trigger = (br_config[21]);
|
assign bw_manual_trigger = (br_config[21]);
|
assign bw_disable_trigger = (br_config[20]);
|
assign bw_disable_trigger = (br_config[20]);
|
| Line 198... |
Line 187... |
|
|
//
|
//
|
// Determine when memory is full and capture is complete
|
// Determine when memory is full and capture is complete
|
//
|
//
|
// Writes take place on the data clock
|
// Writes take place on the data clock
|
reg dr_stopped, dr_past_holdoff;
|
reg dr_stopped;
|
reg [19:0] counter; // This is unsigned
|
reg [19:0] counter; // This is unsigned
|
initial dr_stopped = 1'b0;
|
initial dr_stopped = 1'b0;
|
initial counter = 20'h0000;
|
initial counter = 20'h0000;
|
initial dr_past_holdoff = 1'b0;
|
|
always @(posedge i_clk)
|
|
dr_past_holdoff <= (counter >= bw_holdoff);
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset)
|
if (dw_reset)
|
begin
|
begin
|
counter <= 0;
|
counter <= 0;
|
dr_stopped <= 1'b0;
|
dr_stopped <= 1'b0;
|
end else if ((i_ce)&&(dr_triggered))
|
end else if ((i_ce)&&(dr_triggered))
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
// 20 bits. Else we'd need to add a bit to comparison
|
// 20 bits. Else we'd need to add a bit to comparison
|
// here.
|
// here.
|
if (~dr_stopped)
|
if (counter < bw_holdoff)
|
counter <= counter + 20'h01;
|
counter <= counter + 20'h01;
|
dr_stopped <= (dr_stopped)||(dr_past_holdoff);
|
else
|
|
dr_stopped <= 1'b1;
|
end
|
end
|
|
|
//
|
//
|
// Actually do our writes to memory. Record, via 'primed' when
|
// Actually do our writes to memory. Record, via 'primed' when
|
// the memory is full.
|
// the memory is full.
|
| Line 237... |
Line 224... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset) // For simulation purposes, supply a valid value
|
if (dw_reset) // For simulation purposes, supply a valid value
|
begin
|
begin
|
waddr <= 0; // upon reset.
|
waddr <= 0; // upon reset.
|
dr_primed <= 1'b0;
|
dr_primed <= 1'b0;
|
end else if ((i_ce)&&(~dr_stopped))
|
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
begin
|
begin
|
// mem[waddr] <= i_data;
|
// mem[waddr] <= i_data;
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
dr_primed <= (dr_primed)||(&waddr);
|
dr_primed <= (dr_primed)||(&waddr);
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_ce)&&(~dr_stopped))
|
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
mem[waddr] <= i_data;
|
mem[waddr] <= i_data;
|
|
|
//
|
//
|
// Clock transfer of the status signals
|
// Clock transfer of the status signals
|
//
|
//
|
| Line 282... |
Line 269... |
assign bw_triggered = r_oflags[1];
|
assign bw_triggered = r_oflags[1];
|
assign bw_primed = r_oflags[0];
|
assign bw_primed = r_oflags[0];
|
end endgenerate
|
end endgenerate
|
|
|
// Reads use the bus clock
|
// Reads use the bus clock
|
reg br_wb_ack, r_wb_ack, s_wb_ack; // takes two clock to read
|
reg br_wb_ack;
|
reg s_wb_addr, q_wb_addr;
|
|
reg bw_cyc_stb, bus_read_fifo, bus_write_fifo;
|
|
always @(posedge i_clk)
|
|
bw_cyc_stb = (r_wb_stb);
|
|
always @(posedge i_clk)
|
|
bus_read_fifo <= (r_wb_stb)&&(r_wb_addr)&&(~r_wb_we);
|
|
always @(posedge i_clk)
|
|
bus_write_fifo <= (r_wb_stb)&&(r_wb_addr)&&(r_wb_we);
|
|
initial br_wb_ack = 1'b0;
|
initial br_wb_ack = 1'b0;
|
|
wire bw_cyc_stb;
|
|
assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb));
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
begin // CE depends upon 5 inputs, output on 7 (ignoring add&carries)
|
begin
|
if ((bw_reset_request)||(bus_write_fifo))
|
if ((bw_reset_request)
|
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
raddr <= 0;
|
raddr <= 0;
|
else if ((bus_read_fifo)&&(bw_stopped))
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
|
raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped
|
raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped
|
|
|
r_wb_ack <= r_wb_stb;
|
if ((bw_cyc_stb)&&(~i_wb_we))
|
s_wb_ack <= r_wb_ack;
|
begin // Read from the bus
|
br_wb_ack <= s_wb_ack;
|
br_wb_ack <= 1'b1;
|
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
|
// We did this write above
|
|
br_wb_ack <= 1'b1;
|
|
else // Do nothing if either i_wb_cyc or i_wb_stb are low
|
|
br_wb_ack <= 1'b0;
|
end
|
end
|
|
|
reg [(LGMEM-1):0] nxt_addr;
|
|
always @(posedge i_wb_clk) // 2 adds, then 5 inputs
|
|
if (bus_read_fifo)
|
|
nxt_addr <= nxt_addr + {{(LGMEM-1){1'b0}},1'b1};
|
|
else
|
|
nxt_addr <= raddr + waddr;
|
|
// nxt_addr <= raddr + waddr + (bus_read_fifo)
|
|
// ? {{(LGMEM-1){1'b0}},1'b1}: 0;
|
|
|
|
reg [31:0] nxt_mem;
|
reg [31:0] nxt_mem;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
nxt_mem <= mem[nxt_addr];
|
nxt_mem <= mem[raddr+waddr+
|
|
(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
|
always @(posedge i_clk)
|
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
|
s_wb_addr <= r_wb_addr;
|
|
always @(posedge i_clk)
|
|
q_wb_addr <= s_wb_addr;
|
|
|
|
wire [4:0] bw_lgmem;
|
wire [4:0] bw_lgmem;
|
assign bw_lgmem = LGMEM;
|
assign bw_lgmem = LGMEM;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if (~q_wb_addr) // Control register read
|
if (~i_wb_addr) // Control register read
|
o_wb_data <= { bw_reset_request,
|
o_wb_data <= { bw_reset_request,
|
bw_stopped,
|
bw_stopped,
|
bw_triggered,
|
bw_triggered,
|
bw_primed,
|
bw_primed,
|
bw_manual_trigger,
|
bw_manual_trigger,
|
| Line 341... |
Line 316... |
o_wb_data <= i_data;
|
o_wb_data <= i_data;
|
else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
assign o_wb_ack = (s_wb_ack);
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
|
|
reg br_level_interrupt;
|
reg br_level_interrupt;
|
initial br_level_interrupt = 1'b0;
|
initial br_level_interrupt = 1'b0;
|
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
|
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
|
&&(~br_level_interrupt);
|
&&(~br_level_interrupt);
|
