| Line 78... |
Line 78... |
../bin/msp430sim clock_module_asic | tee ./log/clock_module_asic.log
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../bin/msp430sim clock_module_asic | tee ./log/clock_module_asic.log
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../bin/msp430sim clock_module_asic_mclk | tee ./log/clock_module_asic_mclk.log
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../bin/msp430sim clock_module_asic_mclk | tee ./log/clock_module_asic_mclk.log
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../bin/msp430sim clock_module_asic_smclk | tee ./log/clock_module_asic_smclk.log
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../bin/msp430sim clock_module_asic_smclk | tee ./log/clock_module_asic_smclk.log
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../bin/msp430sim clock_module_asic_lfxt | tee ./log/clock_module_asic_lfxt.log
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../bin/msp430sim clock_module_asic_lfxt | tee ./log/clock_module_asic_lfxt.log
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# Serial Debug Interface
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# Serial Debug Interface (UART)
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../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log
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../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log
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../bin/msp430sim dbg_uart_sync | tee ./log/dbg_uart_sync.log
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../bin/msp430sim dbg_uart_sync | tee ./log/dbg_uart_sync.log
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../bin/msp430sim dbg_cpu | tee ./log/dbg_cpu.log
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../bin/msp430sim dbg_uart_cpu | tee ./log/dbg_uart_cpu.log
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../bin/msp430sim dbg_mem | tee ./log/dbg_mem.log
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../bin/msp430sim dbg_uart_mem | tee ./log/dbg_uart_mem.log
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../bin/msp430sim dbg_hwbrk0 | tee ./log/dbg_hwbrk0.log
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../bin/msp430sim dbg_uart_hwbrk0 | tee ./log/dbg_uart_hwbrk0.log
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../bin/msp430sim dbg_hwbrk1 | tee ./log/dbg_hwbrk1.log
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../bin/msp430sim dbg_uart_hwbrk1 | tee ./log/dbg_uart_hwbrk1.log
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../bin/msp430sim dbg_hwbrk2 | tee ./log/dbg_hwbrk2.log
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../bin/msp430sim dbg_uart_hwbrk2 | tee ./log/dbg_uart_hwbrk2.log
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../bin/msp430sim dbg_hwbrk3 | tee ./log/dbg_hwbrk3.log
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../bin/msp430sim dbg_uart_hwbrk3 | tee ./log/dbg_uart_hwbrk3.log
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../bin/msp430sim dbg_rdwr | tee ./log/dbg_rdwr.log
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../bin/msp430sim dbg_uart_rdwr | tee ./log/dbg_uart_rdwr.log
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../bin/msp430sim dbg_halt_irq | tee ./log/dbg_halt_irq.log
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../bin/msp430sim dbg_uart_halt_irq | tee ./log/dbg_uart_halt_irq.log
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../bin/msp430sim dbg_onoff | tee ./log/dbg_onoff.log
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../bin/msp430sim dbg_uart_onoff | tee ./log/dbg_uart_onoff.log
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../bin/msp430sim dbg_onoff_asic | tee ./log/dbg_onoff_asic.log
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../bin/msp430sim dbg_uart_onoff_asic | tee ./log/dbg_uart_onoff_asic.log
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# Serial Debug Interface (I2C)
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../bin/msp430sim dbg_i2c | tee ./log/dbg_i2c.log
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../bin/msp430sim dbg_i2c_sync | tee ./log/dbg_i2c_sync.log
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../bin/msp430sim dbg_i2c_cpu | tee ./log/dbg_i2c_cpu.log
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../bin/msp430sim dbg_i2c_mem | tee ./log/dbg_i2c_mem.log
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../bin/msp430sim dbg_i2c_hwbrk0 | tee ./log/dbg_i2c_hwbrk0.log
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../bin/msp430sim dbg_i2c_hwbrk1 | tee ./log/dbg_i2c_hwbrk1.log
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../bin/msp430sim dbg_i2c_hwbrk2 | tee ./log/dbg_i2c_hwbrk2.log
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../bin/msp430sim dbg_i2c_hwbrk3 | tee ./log/dbg_i2c_hwbrk3.log
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../bin/msp430sim dbg_i2c_rdwr | tee ./log/dbg_i2c_rdwr.log
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../bin/msp430sim dbg_i2c_halt_irq | tee ./log/dbg_i2c_halt_irq.log
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../bin/msp430sim dbg_i2c_onoff | tee ./log/dbg_i2c_onoff.log
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../bin/msp430sim dbg_i2c_onoff_asic | tee ./log/dbg_i2c_onoff_asic.log
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# SFR test patterns
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# SFR test patterns
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../bin/msp430sim sfr | tee ./log/sfr.log
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../bin/msp430sim sfr | tee ./log/sfr.log
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|
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# SCAN test patterns (only to increase coverage)
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# SCAN test patterns (only to increase coverage)
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| Line 119... |
Line 133... |
../bin/msp430sim tA_compare | tee ./log/tA_compare.log
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../bin/msp430sim tA_compare | tee ./log/tA_compare.log
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../bin/msp430sim tA_output | tee ./log/tA_output.log
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../bin/msp430sim tA_output | tee ./log/tA_output.log
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../bin/msp430sim tA_capture | tee ./log/tA_capture.log
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../bin/msp430sim tA_capture | tee ./log/tA_capture.log
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../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log
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../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log
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# Simple full duplex UART (8N1 protocol)
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#../bin/msp430sim uart | tee ./log/uart.log
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# Hardware multiplier test patterns
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# Hardware multiplier test patterns
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../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log
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../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log
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# Report regression results
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# Report regression results
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../bin/parse_results
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../bin/parse_results
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