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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: registers.v
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// *File Name: registers.v
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//
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//
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// *Module Description:
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// *Module Description:
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// openMSP430 testbench
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// Direct connections to internal registers & memory.
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//
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 111 $
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// $Rev: 136 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// CPU registers
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// CPU registers
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//======================
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//======================
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wire [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
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wire [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
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wire [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
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wire [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
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wire [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
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wire [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
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// Interrupt detection
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wire nmi_detect = dut.openMSP430_0.frontend_0.nmi_pnd;
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wire irq_detect = dut.openMSP430_0.frontend_0.irq_detect;
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// Debug interface
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wire dbg_en = dut.openMSP430_0.dbg_en;
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wire dbg_clk = dut.openMSP430_0.clock_module_0.dbg_clk;
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wire dbg_rst = dut.openMSP430_0.clock_module_0.dbg_rst;
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// CPU internals
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// CPU internals
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//======================
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//======================
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wire mclk = dut.openMSP430_0.mclk;
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wire mclk = dut.openMSP430_0.mclk;
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wire puc_rst = dut.openMSP430_0.puc_rst;
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wire puc_rst = dut.openMSP430_0.puc_rst;
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