| Line 265... |
Line 265... |
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
trace_trap <= #1 1'b0 ;
|
trace_trap <= 1'b0 ;
|
end
|
end
|
else if (!(trace_trap && !ex_pc_val)) begin
|
else if (!(trace_trap && !ex_pc_val)) begin
|
trace_trap <= #1 trace_cond & !dsr_te & !sr_ted ;
|
trace_trap <= trace_cond & !dsr_te & !sr_ted ;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_freeze_prev <= #1 1'b0 ;
|
ex_freeze_prev <= 1'b0 ;
|
sr_ted_prev <= #1 1'b0 ;
|
sr_ted_prev <= 1'b0 ;
|
dsr_te_prev <= #1 1'b0 ;
|
dsr_te_prev <= 1'b0 ;
|
dmr1_st_prev <= #1 1'b0 ;
|
dmr1_st_prev <= 1'b0 ;
|
dmr1_bt_prev <= #1 1'b0 ;
|
dmr1_bt_prev <= 1'b0 ;
|
end
|
end
|
else begin
|
else begin
|
ex_freeze_prev <= #1 ex_freeze ;
|
ex_freeze_prev <= ex_freeze ;
|
if (!ex_freeze_prev || ex_void) begin
|
if (!ex_freeze_prev || ex_void) begin
|
sr_ted_prev <= #1 sr [`OR1200_SR_TED ] ;
|
sr_ted_prev <= sr [`OR1200_SR_TED ] ;
|
dsr_te_prev <= #1 du_dsr [`OR1200_DU_DSR_TE ] ;
|
dsr_te_prev <= du_dsr [`OR1200_DU_DSR_TE ] ;
|
dmr1_st_prev <= #1 du_dmr1[`OR1200_DU_DMR1_ST] ;
|
dmr1_st_prev <= du_dmr1[`OR1200_DU_DMR1_ST] ;
|
dmr1_bt_prev <= #1 du_dmr1[`OR1200_DU_DMR1_BT] ;
|
dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
id_pc <= #1 32'd0;
|
id_pc <= 32'd0;
|
id_pc_val <= #1 1'b0 ;
|
id_pc_val <= 1'b0 ;
|
id_exceptflags <= #1 3'b000;
|
id_exceptflags <= 3'b000;
|
end
|
end
|
else if (id_flushpipe) begin
|
else if (id_flushpipe) begin
|
id_pc_val <= #1 1'b0 ;
|
id_pc_val <= 1'b0 ;
|
id_exceptflags <= #1 3'b000;
|
id_exceptflags <= 3'b000;
|
end
|
end
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_pc <= #1 if_pc;
|
id_pc <= if_pc;
|
id_pc_val <= #1 1'b1 ;
|
id_pc_val <= 1'b1 ;
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// delayed_iee
|
// delayed_iee
|
| Line 321... |
Line 321... |
// together with SR[IEE] enables interrupts once
|
// together with SR[IEE] enables interrupts once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
if (rst)
|
if (rst)
|
delayed_iee <= #1 3'b000;
|
delayed_iee <= 3'b000;
|
else if (!sr[`OR1200_SR_IEE])
|
else if (!sr[`OR1200_SR_IEE])
|
delayed_iee <= #1 3'b000;
|
delayed_iee <= 3'b000;
|
else
|
else
|
delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
|
delayed_iee <= {delayed_iee[1:0], 1'b1};
|
|
|
//
|
//
|
// delayed_tee
|
// delayed_tee
|
//
|
//
|
// SR[TEE] should not enable tick exceptions right away
|
// SR[TEE] should not enable tick exceptions right away
|
| Line 337... |
Line 337... |
// together with SR[TEE] enables tick exceptions once
|
// together with SR[TEE] enables tick exceptions once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
if (rst)
|
if (rst)
|
delayed_tee <= #1 3'b000;
|
delayed_tee <= 3'b000;
|
else if (!sr[`OR1200_SR_TEE])
|
else if (!sr[`OR1200_SR_TEE])
|
delayed_tee <= #1 3'b000;
|
delayed_tee <= 3'b000;
|
else
|
else
|
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
|
delayed_tee <= {delayed_tee[1:0], 1'b1};
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= 1'b0;
|
ex_pc <= #1 32'd0;
|
ex_pc <= 32'd0;
|
ex_pc_val <= #1 1'b0 ;
|
ex_pc_val <= 1'b0 ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= 1'b0;
|
end
|
end
|
else if (ex_flushpipe) begin
|
else if (ex_flushpipe) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= 1'b0;
|
ex_pc_val <= #1 1'b0 ;
|
ex_pc_val <= 1'b0 ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze) begin
|
else if (!ex_freeze & id_freeze) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= 1'b0;
|
ex_pc <= #1 id_pc;
|
ex_pc <= id_pc;
|
ex_pc_val <= #1 id_pc_val ;
|
ex_pc_val <= id_pc_val ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= 3'b000;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= delayed1_ex_dslot;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_dslot <= #1 ex_branch_taken;
|
ex_dslot <= ex_branch_taken;
|
ex_pc <= #1 id_pc;
|
ex_pc <= id_pc;
|
ex_pc_val <= #1 id_pc_val ;
|
ex_pc_val <= id_pc_val ;
|
ex_exceptflags <= #1 id_exceptflags;
|
ex_exceptflags <= id_exceptflags;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= delayed1_ex_dslot;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
wb_pc <= #1 32'd0;
|
wb_pc <= 32'd0;
|
dl_pc <= #1 32'd0;
|
dl_pc <= 32'd0;
|
end
|
end
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_pc <= #1 ex_pc;
|
wb_pc <= ex_pc;
|
dl_pc <= #1 wb_pc;
|
dl_pc <= wb_pc;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// We have started execution of exception handler:
|
// We have started execution of exception handler:
|
| Line 409... |
Line 409... |
// except_type signals which exception handler we start fetching in:
|
// except_type signals which exception handler we start fetching in:
|
// 1. Asserted in next clock cycle after exception is recognized
|
// 1. Asserted in next clock cycle after exception is recognized
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= 1'b0;
|
epcr <= #1 32'b0;
|
epcr <= 32'b0;
|
eear <= #1 32'b0;
|
eear <= 32'b0;
|
esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
`else
|
`else
|
case (state) // synopsys full_case parallel_case
|
case (state) // synopsys full_case parallel_case
|
`endif
|
`endif
|
`OR1200_EXCEPTFSM_IDLE:
|
`OR1200_EXCEPTFSM_IDLE:
|
if (except_flushpipe) begin
|
if (except_flushpipe) begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
state <= `OR1200_EXCEPTFSM_FLU1;
|
extend_flush <= #1 1'b1;
|
extend_flush <= 1'b1;
|
esr <= #1 sr_we ? to_sr : sr;
|
esr <= sr_we ? to_sr : sr;
|
casex (except_trig)
|
casex (except_trig)
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
14'b1x_xxxx_xxxx_xxxx: begin
|
14'b1x_xxxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
except_type <= `OR1200_EXCEPT_ITLBMISS;
|
eear <= #1 ex_dslot ?
|
eear <= ex_dslot ?
|
ex_pc : ex_pc;
|
ex_pc : ex_pc;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_IPF
|
`ifdef OR1200_EXCEPT_IPF
|
14'b01_xxxx_xxxx_xxxx: begin
|
14'b01_xxxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
except_type <= `OR1200_EXCEPT_IPF;
|
eear <= #1 ex_dslot ?
|
eear <= ex_dslot ?
|
ex_pc : delayed1_ex_dslot ?
|
ex_pc : delayed1_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : id_pc;
|
id_pc : id_pc;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : id_pc;
|
id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error
|
14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
eear <= #1 ex_dslot ?
|
eear <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
14'b00_01xx_xxxx_xxxx: begin
|
14'b00_01xx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
|
except_type <= `OR1200_EXCEPT_ILLEGAL;
|
eear <= #1 ex_pc;
|
eear <= ex_pc;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ALIGN
|
`ifdef OR1200_EXCEPT_ALIGN
|
14'b00_001x_xxxx_xxxx: begin
|
14'b00_001x_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ALIGN;
|
except_type <= `OR1200_EXCEPT_ALIGN;
|
eear <= #1 lsu_addr;
|
eear <= lsu_addr;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : ex_pc;
|
wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
14'b00_0001_xxxx_xxxx: begin
|
14'b00_0001_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
except_type <= `OR1200_EXCEPT_DTLBMISS;
|
eear <= #1 lsu_addr;
|
eear <= lsu_addr;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : ex_pc;
|
dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TRAP
|
`ifdef OR1200_EXCEPT_TRAP
|
14'b00_0000_1xxx_xxxx: begin
|
14'b00_0000_1xxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
except_type <= `OR1200_EXCEPT_TRAP;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : ex_pc;
|
id_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_SYSCALL
|
`ifdef OR1200_EXCEPT_SYSCALL
|
14'b00_0000_01xx_xxxx: begin
|
14'b00_0000_01xx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
except_type <= `OR1200_EXCEPT_SYSCALL;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : id_pc;
|
id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DPF
|
`ifdef OR1200_EXCEPT_DPF
|
14'b00_0000_001x_xxxx: begin
|
14'b00_0000_001x_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
except_type <= `OR1200_EXCEPT_DPF;
|
eear <= #1 lsu_addr;
|
eear <= lsu_addr;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : ex_pc;
|
dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
14'b00_0000_0001_xxxx: begin // Data Bus Error
|
14'b00_0000_0001_xxxx: begin // Data Bus Error
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= `OR1200_EXCEPT_BUSERR;
|
eear <= #1 lsu_addr;
|
eear <= lsu_addr;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
dl_pc : ex_pc;
|
dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_RANGE
|
`ifdef OR1200_EXCEPT_RANGE
|
14'b00_0000_0000_1xxx: begin
|
14'b00_0000_0000_1xxx: begin
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
except_type <= `OR1200_EXCEPT_RANGE;
|
epcr <= #1 ex_dslot ?
|
epcr <= ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
wb_pc : delayed1_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : delayed2_ex_dslot ?
|
id_pc : id_pc;
|
id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_FLOAT
|
`ifdef OR1200_EXCEPT_FLOAT
|
14'b00_0000_0000_01xx: begin
|
14'b00_0000_0000_01xx: begin
|
except_type <= #1 `OR1200_EXCEPT_FLOAT;
|
except_type <= `OR1200_EXCEPT_FLOAT;
|
epcr <= #1 id_pc;
|
epcr <= id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_INT
|
`ifdef OR1200_EXCEPT_INT
|
14'b00_0000_0000_001x: begin
|
14'b00_0000_0000_001x: begin
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
except_type <= `OR1200_EXCEPT_INT;
|
epcr <= #1 id_pc;
|
epcr <= id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TICK
|
`ifdef OR1200_EXCEPT_TICK
|
14'b00_0000_0000_0001: begin
|
14'b00_0000_0000_0001: begin
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
except_type <= `OR1200_EXCEPT_TICK;
|
epcr <= #1 id_pc;
|
epcr <= id_pc;
|
end
|
end
|
`endif
|
`endif
|
default:
|
default:
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
endcase
|
endcase
|
end
|
end
|
else if (pc_we) begin
|
else if (pc_we) begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
state <= `OR1200_EXCEPTFSM_FLU1;
|
extend_flush <= #1 1'b1;
|
extend_flush <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if (epcr_we)
|
if (epcr_we)
|
epcr <= #1 datain;
|
epcr <= datain;
|
if (eear_we)
|
if (eear_we)
|
eear <= #1 datain;
|
eear <= datain;
|
if (esr_we)
|
if (esr_we)
|
esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
|
esr <= {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU1:
|
`OR1200_EXCEPTFSM_FLU1:
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
state <= `OR1200_EXCEPTFSM_FLU2;
|
`OR1200_EXCEPTFSM_FLU2:
|
`OR1200_EXCEPTFSM_FLU2:
|
`ifdef OR1200_EXCEPT_TRAP
|
`ifdef OR1200_EXCEPT_TRAP
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= 1'b0;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= 1'b0;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
state <= #1 `OR1200_EXCEPTFSM_FLU3;
|
state <= `OR1200_EXCEPTFSM_FLU3;
|
`OR1200_EXCEPTFSM_FLU3:
|
`OR1200_EXCEPTFSM_FLU3:
|
begin
|
begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU4;
|
state <= `OR1200_EXCEPTFSM_FLU4;
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU4: begin
|
`OR1200_EXCEPTFSM_FLU4: begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU5;
|
state <= `OR1200_EXCEPTFSM_FLU5;
|
extend_flush <= #1 1'b0;
|
extend_flush <= 1'b0;
|
extend_flush_last <= #1 1'b0; // damjan
|
extend_flush_last <= 1'b0; // damjan
|
end
|
end
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
default: begin
|
default: begin
|
`else
|
`else
|
`OR1200_EXCEPTFSM_FLU5: begin
|
`OR1200_EXCEPTFSM_FLU5: begin
|
`endif
|
`endif
|
if (!if_stall && !id_freeze) begin
|
if (!if_stall && !id_freeze) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= `OR1200_EXCEPT_NONE;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= 1'b0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
