URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_fpu.v] - Diff between revs 185 and 186

Rev 185	Rev 186
Line 114...	Line 114...
`input spr_write;`	`input spr_write;`
`input [31:0] spr_addr;`	`input [31:0] spr_addr;`
`input [31:0] spr_dat_i;`	`input [31:0] spr_dat_i;`
`output [31:0] spr_dat_o;`	`output [31:0] spr_dat_o;`


	`ifndef OR1200_FPU_IMPLEMENTED

	`// No FPU needed`
	`assign result = 0;`
	`assign flagforw = 0;`
	`assign flag_we = 0;`
	`assign sig_fp = 0;`
	`assign spr_dat_o = 0;`

	`else


`//`	`//`
`// Internals`	`// Internals`
`//`	`//`
`reg [2:0] fpu_op_count;`	`reg [2:0] fpu_op_count;`
reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r;	reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r;
Line 130...	Line 143...
`wire fpu_op_is_comp, fpu_op_r_is_comp;`	`wire fpu_op_is_comp, fpu_op_r_is_comp;`
`wire altb, blta, aeqb, cmp_inf, cmp_zero,`	`wire altb, blta, aeqb, cmp_inf, cmp_zero,`
`unordered ;`	`unordered ;`
`reg flag;`	`reg flag;`


`assign fpcsr = fpcsr_r;`	`assign fpcsr = fpcsr_r;`

assign sig_fp = fpcsr_r[`OR1200_FPCSR_FPEE]	assign sig_fp = fpcsr_r[`OR1200_FPCSR_FPEE]
& (\|fpcsr_r[`OR1200_FPCSR_WIDTH-1:`OR1200_FPCSR_OVF]);	& (\|fpcsr_r[`OR1200_FPCSR_WIDTH-1:`OR1200_FPCSR_OVF]);

Line 275...	Line 289...
`.blta(altb),`	`.blta(altb),`
`.aeqb(aeqb),`	`.aeqb(aeqb),`
`.inf(cmp_inf),`	`.inf(cmp_inf),`
`.zero(cmp_zero));`	`.zero(cmp_zero));`

	`endif // !`ifndef OR1200_FPU_IMPLEMENTED

`endmodule // or1200_fpu`	`endmodule // or1200_fpu`

`No newline at end of file`	`No newline at end of file`