URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Diff between revs 10 and 141

Rev 10	Rev 141
Line 41...	Line 41...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_ic_top.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// No update`
	`//`
	`// Revision 1.9 2004/04/05 08:29:57 lampret`
	`// Merged branch_qmem into main tree.`
	`//`
`// Revision 1.7.4.2 2003/12/09 11:46:48 simons`	`// Revision 1.7.4.2 2003/12/09 11:46:48 simons`
`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`	`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
`//`	`//`
`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`	`// Revision 1.7.4.1 2003/07/08 15:36:37 lampret`
`// Added embedded memory QMEM.`	`// Added embedded memory QMEM.`