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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's instruction fetch ////
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//// OR1200's instruction fetch ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// PC, instruction fetch, interface to IC. ////
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//// PC, instruction fetch, interface to IC. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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// $Log: or1200_if.v,v $
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// $Log: or1200_if.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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// Revision 1.5 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.3 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Break point bug fixed
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//
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// Revision 1.9 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.8 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.7 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.1 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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//
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//
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assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
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assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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if_bypass_reg <= #1 1'b0;
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if_bypass_reg <= 1'b0;
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else
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else
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if_bypass_reg <= #1 if_bypass;
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if_bypass_reg <= if_bypass;
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//
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//
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// IF stage insn
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// IF stage insn
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//
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//
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assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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//
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//
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// Flag for saved insn/address
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// Flag for saved insn/address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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saved <= #1 1'b0;
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saved <= 1'b0;
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else if (if_flushpipe)
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else if (if_flushpipe)
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saved <= #1 1'b0;
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saved <= 1'b0;
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else if (save_insn)
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else if (save_insn)
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saved <= #1 1'b1;
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saved <= 1'b1;
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else if (!if_freeze)
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else if (!if_freeze)
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saved <= #1 1'b0;
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saved <= 1'b0;
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//
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//
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// Store fetched instruction
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// Store fetched instruction
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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else if (if_flushpipe)
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else if (if_flushpipe)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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else if (save_insn)
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else if (save_insn)
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insn_saved <= #1 icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
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insn_saved <= icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
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else if (!if_freeze)
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else if (!if_freeze)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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//
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//
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// Store fetched instruction's address
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// Store fetched instruction's address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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addr_saved <= #1 32'h00000000;
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addr_saved <= 32'h00000000;
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else if (if_flushpipe)
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else if (if_flushpipe)
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addr_saved <= #1 32'h00000000;
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addr_saved <= 32'h00000000;
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else if (save_insn)
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else if (save_insn)
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addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
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addr_saved <= {icpu_adr_i[31:2], 2'b00};
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else if (!if_freeze)
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else if (!if_freeze)
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addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
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addr_saved <= {icpu_adr_i[31:2], 2'b00};
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//
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//
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// Store fetched instruction's error tags
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// Store fetched instruction's error tags
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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err_saved <= #1 3'b000;
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err_saved <= 3'b000;
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else if (if_flushpipe)
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else if (if_flushpipe)
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err_saved <= #1 3'b000;
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err_saved <= 3'b000;
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else if (save_insn) begin
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else if (save_insn) begin
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err_saved[0] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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err_saved[0] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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err_saved[1] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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err_saved[1] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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err_saved[2] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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err_saved[2] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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end
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end
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else if (!if_freeze)
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else if (!if_freeze)
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err_saved <= #1 3'b000;
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err_saved <= 3'b000;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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