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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_if.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.5 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.3 2002/03/29 15:16:56 lampret
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// Revision 1.3 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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Line 94... |
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// External i/f to IC
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// External i/f to IC
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icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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// Internal i/f
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// Internal i/f
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if_freeze, if_insn, if_pc, flushpipe,
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if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,
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if_stall, no_more_dslot, genpc_refetch, rfe,
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if_stall, no_more_dslot, genpc_refetch, rfe,
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except_itlbmiss, except_immufault, except_ibuserr
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except_itlbmiss, except_immufault, except_ibuserr
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);
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);
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input if_freeze;
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input if_freeze;
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output [31:0] if_insn;
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output [31:0] if_insn;
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output [31:0] if_pc;
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output [31:0] if_pc;
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input flushpipe;
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input if_flushpipe;
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output saving_if_insn;
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output if_stall;
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output if_stall;
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input no_more_dslot;
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input no_more_dslot;
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output genpc_refetch;
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output genpc_refetch;
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input rfe;
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input rfe;
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output except_itlbmiss;
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output except_itlbmiss;
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output except_ibuserr;
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output except_ibuserr;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire save_insn;
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wire if_bypass;
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reg if_bypass_reg;
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reg [31:0] insn_saved;
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reg [31:0] insn_saved;
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reg [31:0] addr_saved;
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reg [31:0] addr_saved;
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reg [2:0] err_saved;
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reg saved;
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reg saved;
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assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved;
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assign saving_if_insn = !if_flushpipe & save_insn;
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//
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// IF bypass
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//
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assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
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always @(posedge clk or posedge rst)
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if (rst)
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if_bypass_reg <= #1 1'b0;
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else
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if_bypass_reg <= #1 if_bypass;
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//
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//
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// IF stage insn
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// IF stage insn
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//
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//
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assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_pc = saved ? addr_saved : icpu_adr_i;
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assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};
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// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign genpc_refetch = saved & icpu_ack_i;
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assign genpc_refetch = saved & icpu_ack_i;
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assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
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assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
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assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
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assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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//
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//
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// Flag for saved insn/address
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// Flag for saved insn/address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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saved <= #1 1'b0;
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saved <= #1 1'b0;
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else if (flushpipe)
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else if (if_flushpipe)
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saved <= #1 1'b0;
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saved <= #1 1'b0;
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else if (icpu_ack_i & if_freeze & !saved)
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else if (save_insn)
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saved <= #1 1'b1;
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saved <= #1 1'b1;
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else if (!if_freeze)
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else if (!if_freeze)
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saved <= #1 1'b0;
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saved <= #1 1'b0;
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//
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//
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// Store fetched instruction
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// Store fetched instruction
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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else if (flushpipe)
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else if (if_flushpipe)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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else if (icpu_ack_i & if_freeze & !saved)
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else if (save_insn)
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insn_saved <= #1 icpu_dat_i;
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insn_saved <= #1 icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
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else if (!if_freeze)
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else if (!if_freeze)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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//
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//
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// Store fetched instruction's address
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// Store fetched instruction's address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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addr_saved <= #1 32'h00000000;
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addr_saved <= #1 32'h00000000;
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else if (flushpipe)
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else if (if_flushpipe)
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addr_saved <= #1 32'h00000000;
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addr_saved <= #1 32'h00000000;
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else if (icpu_ack_i & if_freeze & !saved)
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else if (save_insn)
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addr_saved <= #1 icpu_adr_i;
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addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
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else if (!if_freeze)
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addr_saved <= #1 {icpu_adr_i[31:2], 2'b00};
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//
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// Store fetched instruction's error tags
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//
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always @(posedge clk or posedge rst)
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if (rst)
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err_saved <= #1 3'b000;
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else if (if_flushpipe)
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err_saved <= #1 3'b000;
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else if (save_insn) begin
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err_saved[0] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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err_saved[1] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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err_saved[2] <= #1 icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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end
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else if (!if_freeze)
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else if (!if_freeze)
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addr_saved <= #1 icpu_adr_i;
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err_saved <= #1 3'b000;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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