| Line 41... |
Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_immu_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Structure reordered and bugs fixed.
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//
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// Revision 1.15 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Revision 1.14 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.12.4.2 2003/12/09 11:46:48 simons
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// Revision 1.12.4.2 2003/12/09 11:46:48 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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| Line 124... |
Line 131... |
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// CPU i/f
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// CPU i/f
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ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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// SR Interface
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boot_adr_sel_i,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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| Line 163... |
Line 173... |
output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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output icpu_rty_o;
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output icpu_rty_o;
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output icpu_err_o;
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output icpu_err_o;
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//
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//
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// SR Interface
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//
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input boot_adr_sel_i;
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//
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// SPR access
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// SPR access
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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input [aw-1:0] spr_addr;
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input [aw-1:0] spr_addr;
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| Line 205... |
Line 220... |
wire itlb_ci;
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wire itlb_ci;
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wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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wire page_cross;
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wire page_cross;
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reg [31:0] icpu_adr_default;
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wire [31:0] icpu_adr_boot;
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reg icpu_adr_select;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
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`ifdef OR1200_NO_IMMU
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`ifdef OR1200_NO_IMMU
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`else
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`else
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reg itlb_en_r;
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reg itlb_en_r;
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reg dis_spr_access;
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reg dis_spr_access_frst_clk;
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reg dis_spr_access_scnd_clk;
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`endif
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`endif
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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| Line 231... |
Line 250... |
//
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//
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// icpu_adr_o
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// icpu_adr_o
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//
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//
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`ifdef OR1200_REGISTERED_OUTPUTS
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`ifdef OR1200_REGISTERED_OUTPUTS
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always @(posedge rst or posedge clk)
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always @(posedge rst or posedge clk)
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if (rst)
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// default value
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icpu_adr_o <= #1 32'h0000_0100;
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if (rst) begin
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icpu_adr_default <= #1 32'h0000_0100;
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icpu_adr_select <= #1 1'b1; // select async. value due to reset state
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end
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// selected value (different from default) is written into FF after reset state
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else if (icpu_adr_select) begin
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icpu_adr_default <= #1 icpu_adr_boot; // dynamic value can only be assigned to FF out of reset!
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icpu_adr_select <= #1 1'b0; // select FF value
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end
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else begin
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icpu_adr_default <= #1 icpu_adr_i;
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end
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// select async. value for boot address after reset - PC jumps to the address selected after boot!
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//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
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assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
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always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
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if (icpu_adr_select)
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icpu_adr_o = icpu_adr_boot ; // async. value is selected due to reset state
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else
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else
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icpu_adr_o <= #1 icpu_adr_i;
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icpu_adr_o = icpu_adr_default ; // FF value is selected 2nd clock after reset state
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`else
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`else
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Unsupported !!!
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Unsupported !!!
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`endif
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`endif
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//
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//
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| Line 282... |
Line 320... |
// 1200 - 123F itlbmr w0 [63:0]
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// 1200 - 123F itlbmr w0 [63:0]
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//
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//
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// 1300 - 13FF itlbtr w0
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// 1300 - 13FF itlbtr w0
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// 1300 - 133F itlbtr w0 [63:0]
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// 1300 - 133F itlbtr w0 [63:0]
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//
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//
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assign itlb_spr_access = spr_cs & ~dis_spr_access;
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assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
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//
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//
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// Disable ITLB SPR access
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// Disable ITLB SPR access
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//
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//
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// This flop is used to mask ITLB miss/fault exception
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// This flops are used to mask ITLB miss/fault exception
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// during first clock cycle of accessing ITLB SPR. In
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// during first & second clock cycles of accessing ITLB SPR. In
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// subsequent clock cycles it is assumed that ITLB SPR
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// subsequent clock cycles it is assumed that ITLB SPR
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// access was accomplished and that normal instruction fetching
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// access was accomplished and that normal instruction fetching
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// can proceed.
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// can proceed.
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//
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//
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// spr_cs sets dis_spr_access and icpu_rty_o clears it.
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// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
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// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and
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// icpu_rty_o clears it.
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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dis_spr_access <= #1 1'b0;
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dis_spr_access_frst_clk <= #1 1'b0;
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else if (!icpu_rty_o)
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else if (!icpu_rty_o)
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dis_spr_access <= #1 1'b0;
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dis_spr_access_frst_clk <= #1 1'b0;
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else if (spr_cs)
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else if (spr_cs)
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dis_spr_access <= #1 1'b1;
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dis_spr_access_frst_clk <= #1 1'b1;
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always @(posedge clk or posedge rst)
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if (rst)
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dis_spr_access_scnd_clk <= #1 1'b0;
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else if (!icpu_rty_o)
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dis_spr_access_scnd_clk <= #1 1'b0;
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else if (dis_spr_access_frst_clk)
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dis_spr_access_scnd_clk <= #1 1'b1;
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//
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//
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// Tags:
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// Tags:
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//
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//
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// OR1200_DTAG_TE - TLB miss Exception
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// OR1200_ITAG_TE - TLB miss Exception
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// OR1200_DTAG_PE - Page fault Exception
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// OR1200_ITAG_PE - Page fault Exception
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//
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//
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assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
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assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
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//
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//
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// icpu_rty_o
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// icpu_rty_o
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//
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//
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// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
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// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
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assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
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//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
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assign icpu_rty_o = qmemimmu_rty_i;
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//
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//
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// icpu_err_o
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// icpu_err_o
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//
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//
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assign icpu_err_o = miss | fault | qmemimmu_err_i;
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assign icpu_err_o = miss | fault | qmemimmu_err_i;
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| Line 338... |
Line 387... |
// ITLB lookup successful
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// ITLB lookup successful
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//
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//
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assign itlb_done = itlb_en_r & ~page_cross;
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assign itlb_done = itlb_en_r & ~page_cross;
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes
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// use delayed signals.
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// wrong with translation. If IC is disabled, use delayed signals.
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//
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//
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// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
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// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
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assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
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assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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// Cache inhibit is not really needed for instruction memory subsystem.
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// Cache inhibit is not really needed for instruction memory subsystem.
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// If we would doq it, we would doq it like this.
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// If we would doq it, we would doq it like this.
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// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
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// However this causes a async combinational loop so we stick to
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// However this causes an async combinatorial loop so we stick to
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// no cache inhibit.
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// no cache inhibit.
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assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
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// Cache inhibit without an async combinatorial loop
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assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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// simply equal when IMMU is disabled
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//
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//
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assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
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//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
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assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
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reg [31:0] spr_dat_reg;
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//
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//
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// Output to SPRS unit
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// Output to SPRS unit
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//
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//
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assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
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// spr_dat_o is registered on the 1st clock of spr read
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// so itlb can continue with process during execution of mfspr.
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always @(posedge clk or posedge rst)
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if (rst)
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spr_dat_reg <= #1 32'h0000_0000;
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else if (spr_cs & !dis_spr_access_scnd_clk)
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spr_dat_reg <= #1 itlb_dat_o;
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
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//
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//
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// Page fault exception logic
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// Page fault exception logic
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//
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//
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assign fault = itlb_done &
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assign fault = itlb_done &
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