OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_rfram_generic.v] - Diff between revs 10 and 141

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 10 Rev 141
Line 40... Line 40... 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
// $Log: not supported by cvs2svn $
 
//
 
 
 
// $Log: or1200_rfram_generic.v,v $
 
 
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
 
 
// Minor update: 
 
 
// Defines added, coding style changed. 
 
 
//
 
 
 
// Revision 1.3  2004/06/08 18:16:32  lampret
 
 
 
// GPR0 hardwired to zero.
 
 
 
//
 
// Revision 1.2  2002/09/03 22:28:21  lampret
 
// Revision 1.2  2002/09/03 22:28:21  lampret
 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
 
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
 
//
 
//
 
// Revision 1.1  2002/06/08 16:23:30  lampret
 
// Revision 1.1  2002/06/08 16:23:30  lampret
 
// Generic flip-flop based memory macro for register file.
 
// Generic flip-flop based memory macro for register file.
Line 108... Line 116... 
//
 
//
 
// Internal wires and regs
 
// Internal wires and regs
 
//
 
//
 
reg     [aw-1:0]         intaddr_a;
 
reg     [aw-1:0]         intaddr_a;
 
reg     [aw-1:0]         intaddr_b;
 
reg     [aw-1:0]         intaddr_b;
 
 
 
`ifdef OR1200_RFRAM_16REG
 
 
 
reg     [16*dw-1:0]              mem;
 
 
 
`else
 
reg     [32*dw-1:0]              mem;
 
reg     [32*dw-1:0]              mem;
 
 
 
`endif
 
reg     [dw-1:0]         do_a;
 
reg     [dw-1:0]         do_a;
 
reg     [dw-1:0]         do_b;
 
reg     [dw-1:0]         do_b;
 
 
 
 
 
 
 
   // Function to access GPRs (for use by Verilator). No need to hide this one
 
 
 
   // from the simulator, since it has an input (as required by IEEE 1364-2001).
 
 
 
   function [31:0] get_gpr;
 
 
 
      // verilator public
 
 
 
      input [aw-1:0]             gpr_no;
 
 
 
 
 
 
 
      get_gpr = { mem[gpr_no*32 + 31], mem[gpr_no*32 + 30],
 
 
 
                  mem[gpr_no*32 + 29], mem[gpr_no*32 + 28],
 
 
 
                  mem[gpr_no*32 + 27], mem[gpr_no*32 + 26],
 
 
 
                  mem[gpr_no*32 + 25], mem[gpr_no*32 + 24],
 
 
 
                  mem[gpr_no*32 + 23], mem[gpr_no*32 + 22],
 
 
 
                  mem[gpr_no*32 + 21], mem[gpr_no*32 + 20],
 
 
 
                  mem[gpr_no*32 + 19], mem[gpr_no*32 + 18],
 
 
 
                  mem[gpr_no*32 + 17], mem[gpr_no*32 + 16],
 
 
 
                  mem[gpr_no*32 + 15], mem[gpr_no*32 + 14],
 
 
 
                  mem[gpr_no*32 + 13], mem[gpr_no*32 + 12],
 
 
 
                  mem[gpr_no*32 + 11], mem[gpr_no*32 + 10],
 
 
 
                  mem[gpr_no*32 +  9], mem[gpr_no*32 +  8],
 
 
 
                  mem[gpr_no*32 +  7], mem[gpr_no*32 +  6],
 
 
 
                  mem[gpr_no*32 +  5], mem[gpr_no*32 +  4],
 
 
 
                  mem[gpr_no*32 +  3], mem[gpr_no*32 +  2],
 
 
 
                  mem[gpr_no*32 +  1], mem[gpr_no*32 +  0] };
 
 
 
 
 
 
 
   endfunction // get_gpr
 
 
 
 
 
//
 
//
 
// Write port
 
// Write port
 
//
 
//
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
        if (rst) begin
 
        if (rst) begin
 
                mem <= #1 {512'h0, 512'h0};
 
                mem <= #1 {512'h0, 512'h0};
 
        end
 
        end
 
        else if (ce_w & we_w)
 
        else if (ce_w & we_w)
 
                case (addr_w)   // synopsys parallel_case
 
                case (addr_w)   // synopsys parallel_case
 
                        5'd00: mem[32*0+31:32*0] <= #1 32'h0000_0000;
 
 
 
                        5'd01: mem[32*1+31:32*1] <= #1 di_w;
 
                        5'd01: mem[32*1+31:32*1] <= #1 di_w;
 
                        5'd02: mem[32*2+31:32*2] <= #1 di_w;
 
                        5'd02: mem[32*2+31:32*2] <= #1 di_w;
 
                        5'd03: mem[32*3+31:32*3] <= #1 di_w;
 
                        5'd03: mem[32*3+31:32*3] <= #1 di_w;
 
                        5'd04: mem[32*4+31:32*4] <= #1 di_w;
 
                        5'd04: mem[32*4+31:32*4] <= #1 di_w;
 
                        5'd05: mem[32*5+31:32*5] <= #1 di_w;
 
                        5'd05: mem[32*5+31:32*5] <= #1 di_w;
Line 137... Line 173... 
                        5'd11: mem[32*11+31:32*11] <= #1 di_w;
 
                        5'd11: mem[32*11+31:32*11] <= #1 di_w;
 
                        5'd12: mem[32*12+31:32*12] <= #1 di_w;
 
                        5'd12: mem[32*12+31:32*12] <= #1 di_w;
 
                        5'd13: mem[32*13+31:32*13] <= #1 di_w;
 
                        5'd13: mem[32*13+31:32*13] <= #1 di_w;
 
                        5'd14: mem[32*14+31:32*14] <= #1 di_w;
 
                        5'd14: mem[32*14+31:32*14] <= #1 di_w;
 
                        5'd15: mem[32*15+31:32*15] <= #1 di_w;
 
                        5'd15: mem[32*15+31:32*15] <= #1 di_w;
 
 
 
`ifdef OR1200_RFRAM_16REG
 
 
 
`else
 
                        5'd16: mem[32*16+31:32*16] <= #1 di_w;
 
                        5'd16: mem[32*16+31:32*16] <= #1 di_w;
 
                        5'd17: mem[32*17+31:32*17] <= #1 di_w;
 
                        5'd17: mem[32*17+31:32*17] <= #1 di_w;
 
                        5'd18: mem[32*18+31:32*18] <= #1 di_w;
 
                        5'd18: mem[32*18+31:32*18] <= #1 di_w;
 
                        5'd19: mem[32*19+31:32*19] <= #1 di_w;
 
                        5'd19: mem[32*19+31:32*19] <= #1 di_w;
 
                        5'd20: mem[32*20+31:32*20] <= #1 di_w;
 
                        5'd20: mem[32*20+31:32*20] <= #1 di_w;
Line 152... Line 190... 
                        5'd26: mem[32*26+31:32*26] <= #1 di_w;
 
                        5'd26: mem[32*26+31:32*26] <= #1 di_w;
 
                        5'd27: mem[32*27+31:32*27] <= #1 di_w;
 
                        5'd27: mem[32*27+31:32*27] <= #1 di_w;
 
                        5'd28: mem[32*28+31:32*28] <= #1 di_w;
 
                        5'd28: mem[32*28+31:32*28] <= #1 di_w;
 
                        5'd29: mem[32*29+31:32*29] <= #1 di_w;
 
                        5'd29: mem[32*29+31:32*29] <= #1 di_w;
 
                        5'd30: mem[32*30+31:32*30] <= #1 di_w;
 
                        5'd30: mem[32*30+31:32*30] <= #1 di_w;
 
                        default: mem[32*31+31:32*31] <= #1 di_w;
 
                        5'd31: mem[32*31+31:32*31] <= #1 di_w;
 
 
 
`endif
 
 
 
                        default: mem[32*0+31:32*0] <= #1 32'h0000_0000;
 
                endcase
 
                endcase
 
 
 
 
 
//
 
//
 
// Read port A
 
// Read port A
 
//
 
//
Line 167... Line 207... 
        else if (ce_a)
 
        else if (ce_a)
 
                intaddr_a <= #1 addr_a;
 
                intaddr_a <= #1 addr_a;
 
 
 
 
 
always @(mem or intaddr_a)
 
always @(mem or intaddr_a)
 
        case (intaddr_a)        // synopsys parallel_case
 
        case (intaddr_a)        // synopsys parallel_case
 
                5'd00: do_a = 32'h0000_0000;
 
 
 
                5'd01: do_a = mem[32*1+31:32*1];
 
                5'd01: do_a = mem[32*1+31:32*1];
 
                5'd02: do_a = mem[32*2+31:32*2];
 
                5'd02: do_a = mem[32*2+31:32*2];
 
                5'd03: do_a = mem[32*3+31:32*3];
 
                5'd03: do_a = mem[32*3+31:32*3];
 
                5'd04: do_a = mem[32*4+31:32*4];
 
                5'd04: do_a = mem[32*4+31:32*4];
 
                5'd05: do_a = mem[32*5+31:32*5];
 
                5'd05: do_a = mem[32*5+31:32*5];
Line 183... Line 222... 
                5'd11: do_a = mem[32*11+31:32*11];
 
                5'd11: do_a = mem[32*11+31:32*11];
 
                5'd12: do_a = mem[32*12+31:32*12];
 
                5'd12: do_a = mem[32*12+31:32*12];
 
                5'd13: do_a = mem[32*13+31:32*13];
 
                5'd13: do_a = mem[32*13+31:32*13];
 
                5'd14: do_a = mem[32*14+31:32*14];
 
                5'd14: do_a = mem[32*14+31:32*14];
 
                5'd15: do_a = mem[32*15+31:32*15];
 
                5'd15: do_a = mem[32*15+31:32*15];
 
 
 
`ifdef OR1200_RFRAM_16REG
 
 
 
`else
 
                5'd16: do_a = mem[32*16+31:32*16];
 
                5'd16: do_a = mem[32*16+31:32*16];
 
                5'd17: do_a = mem[32*17+31:32*17];
 
                5'd17: do_a = mem[32*17+31:32*17];
 
                5'd18: do_a = mem[32*18+31:32*18];
 
                5'd18: do_a = mem[32*18+31:32*18];
 
                5'd19: do_a = mem[32*19+31:32*19];
 
                5'd19: do_a = mem[32*19+31:32*19];
 
                5'd20: do_a = mem[32*20+31:32*20];
 
                5'd20: do_a = mem[32*20+31:32*20];
Line 198... Line 239... 
                5'd26: do_a = mem[32*26+31:32*26];
 
                5'd26: do_a = mem[32*26+31:32*26];
 
                5'd27: do_a = mem[32*27+31:32*27];
 
                5'd27: do_a = mem[32*27+31:32*27];
 
                5'd28: do_a = mem[32*28+31:32*28];
 
                5'd28: do_a = mem[32*28+31:32*28];
 
                5'd29: do_a = mem[32*29+31:32*29];
 
                5'd29: do_a = mem[32*29+31:32*29];
 
                5'd30: do_a = mem[32*30+31:32*30];
 
                5'd30: do_a = mem[32*30+31:32*30];
 
                default: do_a = mem[32*31+31:32*31];
 
                5'd31: do_a = mem[32*31+31:32*31];
 
 
 
`endif
 
 
 
                default: do_a = 32'h0000_0000;
 
        endcase
 
        endcase
 
 
 
 
 
//
 
//
 
// Read port B
 
// Read port B
 
//
 
//
Line 213... Line 256... 
        else if (ce_b)
 
        else if (ce_b)
 
                intaddr_b <= #1 addr_b;
 
                intaddr_b <= #1 addr_b;
 
 
 
 
 
always @(mem or intaddr_b)
 
always @(mem or intaddr_b)
 
        case (intaddr_b)        // synopsys parallel_case
 
        case (intaddr_b)        // synopsys parallel_case
 
                5'd00: do_b = 32'h0000_0000;
 
 
 
                5'd01: do_b = mem[32*1+31:32*1];
 
                5'd01: do_b = mem[32*1+31:32*1];
 
                5'd02: do_b = mem[32*2+31:32*2];
 
                5'd02: do_b = mem[32*2+31:32*2];
 
                5'd03: do_b = mem[32*3+31:32*3];
 
                5'd03: do_b = mem[32*3+31:32*3];
 
                5'd04: do_b = mem[32*4+31:32*4];
 
                5'd04: do_b = mem[32*4+31:32*4];
 
                5'd05: do_b = mem[32*5+31:32*5];
 
                5'd05: do_b = mem[32*5+31:32*5];
Line 229... Line 271... 
                5'd11: do_b = mem[32*11+31:32*11];
 
                5'd11: do_b = mem[32*11+31:32*11];
 
                5'd12: do_b = mem[32*12+31:32*12];
 
                5'd12: do_b = mem[32*12+31:32*12];
 
                5'd13: do_b = mem[32*13+31:32*13];
 
                5'd13: do_b = mem[32*13+31:32*13];
 
                5'd14: do_b = mem[32*14+31:32*14];
 
                5'd14: do_b = mem[32*14+31:32*14];
 
                5'd15: do_b = mem[32*15+31:32*15];
 
                5'd15: do_b = mem[32*15+31:32*15];
 
 
 
`ifdef OR1200_RFRAM_16REG
 
 
 
`else
 
                5'd16: do_b = mem[32*16+31:32*16];
 
                5'd16: do_b = mem[32*16+31:32*16];
 
                5'd17: do_b = mem[32*17+31:32*17];
 
                5'd17: do_b = mem[32*17+31:32*17];
 
                5'd18: do_b = mem[32*18+31:32*18];
 
                5'd18: do_b = mem[32*18+31:32*18];
 
                5'd19: do_b = mem[32*19+31:32*19];
 
                5'd19: do_b = mem[32*19+31:32*19];
 
                5'd20: do_b = mem[32*20+31:32*20];
 
                5'd20: do_b = mem[32*20+31:32*20];
Line 244... Line 288... 
                5'd26: do_b = mem[32*26+31:32*26];
 
                5'd26: do_b = mem[32*26+31:32*26];
 
                5'd27: do_b = mem[32*27+31:32*27];
 
                5'd27: do_b = mem[32*27+31:32*27];
 
                5'd28: do_b = mem[32*28+31:32*28];
 
                5'd28: do_b = mem[32*28+31:32*28];
 
                5'd29: do_b = mem[32*29+31:32*29];
 
                5'd29: do_b = mem[32*29+31:32*29];
 
                5'd30: do_b = mem[32*30+31:32*30];
 
                5'd30: do_b = mem[32*30+31:32*30];
 
                default: do_b = mem[32*31+31:32*31];
 
                5'd31: do_b = mem[32*31+31:32*31];
 
 
 
`endif
 
 
 
                default: do_b = 32'h0000_0000;
 
        endcase
 
        endcase
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 No newline at end of file
 
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.