URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Diff between revs 408 and 544

Rev 408	Rev 544
Line 101...	Line 101...

`// First, deal with the asychronous reset`	`// First, deal with the asychronous reset`
`wire async_rst;`	`wire async_rst;`
`wire async_rst_n;`	`wire async_rst_n;`

`reset_buffer reset_gbuf`	`assign async_rst_n = rst_n_pad_i;`
`(`
`.GL(async_rst_n),`
`.CLK(rst_n_pad_i)`
`);`

`// Everyone likes active-high reset signals...`	`// Everyone likes active-high reset signals...`
`assign async_rst = ~async_rst_n;`	`assign async_rst = ~async_rst_n;`


`ifdef JTAG_DEBUG	`ifdef JTAG_DEBUG
`gbuf dbg_tck_gbuf`	`assign dbg_tck_o = tck_pad_i;`
`(`
`.CLK(tck_pad_i),`
`.GL(dbg_tck_o)`
`);`
`endif	`endif

`//`	`//`
`// Declare synchronous reset wires here`	`// Declare synchronous reset wires here`
`//`	`//`