| Line 107... |
Line 107... |
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sys_clk_pad_i,
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sys_clk_pad_i,
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rst_n_pad_i
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rst_n_pad_i
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) /* synthesis syn_global_buffers = 8; syn_hier = "flatten" */;
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)/* synthesis syn_global_buffers = 8; */;
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`include "orpsoc-params.v"
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`include "orpsoc-params.v"
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input sys_clk_pad_i;
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input sys_clk_pad_i;
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| Line 1349... |
Line 1349... |
.wbm0_we_i (wbs_i_mc0_we_i ),
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.wbm0_we_i (wbs_i_mc0_we_i ),
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.wbm0_cyc_i (wbs_i_mc0_cyc_i),
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.wbm0_cyc_i (wbs_i_mc0_cyc_i),
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.wbm0_stb_i (wbs_i_mc0_stb_i),
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.wbm0_stb_i (wbs_i_mc0_stb_i),
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.wbm0_dat_o (wbs_i_mc0_dat_o),
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.wbm0_dat_o (wbs_i_mc0_dat_o),
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.wbm0_ack_o (wbs_i_mc0_ack_o),
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.wbm0_ack_o (wbs_i_mc0_ack_o),
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.wbm0_err_o (),
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.wbm0_err_o (wbs_i_mc0_err_o),
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.wbm0_rty_o (),
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.wbm0_rty_o (wbs_i_mc0_rty_o),
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// Wishbone slave interface 1
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// Wishbone slave interface 1
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.wbm1_dat_i (wbs_d_mc0_dat_i),
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.wbm1_dat_i (wbs_d_mc0_dat_i),
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.wbm1_adr_i (wbs_d_mc0_adr_i),
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.wbm1_adr_i (wbs_d_mc0_adr_i),
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.wbm1_sel_i (wbs_d_mc0_sel_i),
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.wbm1_sel_i (wbs_d_mc0_sel_i),
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.wbm1_cti_i (wbs_d_mc0_cti_i),
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.wbm1_cti_i (wbs_d_mc0_cti_i),
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| Line 1362... |
Line 1362... |
.wbm1_we_i (wbs_d_mc0_we_i ),
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.wbm1_we_i (wbs_d_mc0_we_i ),
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.wbm1_cyc_i (wbs_d_mc0_cyc_i),
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.wbm1_cyc_i (wbs_d_mc0_cyc_i),
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.wbm1_stb_i (wbs_d_mc0_stb_i),
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.wbm1_stb_i (wbs_d_mc0_stb_i),
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.wbm1_dat_o (wbs_d_mc0_dat_o),
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.wbm1_dat_o (wbs_d_mc0_dat_o),
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.wbm1_ack_o (wbs_d_mc0_ack_o),
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.wbm1_ack_o (wbs_d_mc0_ack_o),
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.wbm1_err_o (),
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.wbm1_err_o (wbs_d_mc0_err_o),
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.wbm1_rty_o (),
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.wbm1_rty_o (wbs_d_mc0_rty_o),
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// Wishbone slave interface 2
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.wbm2_dat_i (wbm_eth0_dat_o),
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.wbm2_adr_i (wbm_eth0_adr_o),
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.wbm2_sel_i (wbm_eth0_sel_o),
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.wbm2_cti_i (wbm_eth0_cti_o),
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.wbm2_bte_i (wbm_eth0_bte_o),
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.wbm2_we_i (wbm_eth0_we_o ),
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.wbm2_cyc_i (wbm_eth0_cyc_o),
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.wbm2_stb_i (wbm_eth0_stb_o),
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.wbm2_dat_o (wbm_eth0_dat_i),
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.wbm2_ack_o (wbm_eth0_ack_i),
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.wbm2_err_o (wbm_eth0_err_i),
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.wbm2_rty_o (wbm_eth0_rty_i),
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// Clock, reset
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// Clock, reset
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.wb_clk_i (wb_clk),
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.wb_clk_i (wb_clk),
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.wb_rst_i (wb_rst));
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.wb_rst_i (wb_rst));
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assign wbs_i_mc0_err_o = 0;
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assign wbs_i_mc0_rty_o = 0;
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assign wbs_d_mc0_err_o = 0;
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assign wbs_d_mc0_rty_o = 0;
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defparam ram_wb0.aw = wb_aw;
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defparam ram_wb0.aw = wb_aw;
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defparam ram_wb0.dw = wb_dw;
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defparam ram_wb0.dw = wb_dw;
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defparam ram_wb0.mem_span = internal_sram_mem_span;
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defparam ram_wb0.mem_size_bytes = internal_sram_mem_span;
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defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span;
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defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span;
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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`endif // `ifdef RAM_WB
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`endif // `ifdef RAM_WB
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`ifdef ETH0
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`ifdef ETH0
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