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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] [include/] [eth_stim.v] - Diff between revs 485 and 530

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Rev 485 Rev 530
Line 78... Line 78...
parameter eth_stim_num_rx_only_packet_size_change_amount = 127;
parameter eth_stim_num_rx_only_packet_size_change_amount = 127;
parameter eth_stim_num_rx_only_IPG = 800_000; // ps
parameter eth_stim_num_rx_only_IPG = 800_000; // ps
 
 
// Do call/response test
// Do call/response test
reg eth_stim_do_rx_reponse_to_tx;
reg eth_stim_do_rx_reponse_to_tx;
 
reg eth_stim_do_overflow_test;
 
 
parameter num_tx_bds = 16;
parameter num_tx_bds = 16;
parameter num_tx_bds_mask = 4'hf;
parameter num_tx_bds_mask = 4'hf;
parameter num_rx_bds = 16;
parameter num_rx_bds = 16;
parameter num_rx_bds_mask = 4'hf;
parameter num_rx_bds_mask = 4'hf;
Line 147... Line 147...
 
 
     eth_stim_waiting = 1;
     eth_stim_waiting = 1;
     expected_rxbd = num_tx_bds; // init this here
     expected_rxbd = num_tx_bds; // init this here
 
 
     eth_stim_do_rx_reponse_to_tx = 0;
     eth_stim_do_rx_reponse_to_tx = 0;
 
     eth_stim_do_overflow_test = 0;
 
 
     while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
     while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
       begin
       begin
          #100;
          #100;
          // If RX enable and not TX enable...
          // If RX enable and not TX enable...
Line 175... Line 175...
                                     eth_stim_num_rx_only_packet_size_change,
                                     eth_stim_num_rx_only_packet_size_change,
                                     eth_stim_num_rx_only_packet_size_change_amount,
                                     eth_stim_num_rx_only_packet_size_change_amount,
                                     eth_phy0.eth_speed,     // Speed
                                     eth_phy0.eth_speed,     // Speed
                                     eth_stim_num_rx_only_IPG, // IPG
                                     eth_stim_num_rx_only_IPG, // IPG
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
                               0, 0);
                               0, 0, 0);
 
 
                    eth_stim_waiting = 0;
                    eth_stim_waiting = 0;
                 end
                 end
            end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
            end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
          // If both RX and TX enabled
          // If both RX and TX enabled
Line 197... Line 197...
                   0:
                   0:
                     begin
                     begin
                        // kickoff call/response here
                        // kickoff call/response here
                        eth_stim_do_rx_reponse_to_tx = 1;
                        eth_stim_do_rx_reponse_to_tx = 1;
                     end
                     end
 
                   1:
 
                     begin
 
                        // kickoff overflow test here
 
                        eth_stim_do_overflow_test = 1;
 
                     end
                   default:
                   default:
                     begin
                     begin
                        do_rx_while_tx_stim(1400);
                        do_rx_while_tx_stim(1400);
                     end
                     end
                 endcase // case (eth_phy0.tx_mem[0])
                 endcase // case (eth_phy0.tx_mem[0])
Line 225... Line 230...
           begin
           begin
 
 
              send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
              send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
                               speed_loop[0], 10000,
                               speed_loop[0], 10000,
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
                               48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
                               inject_errors, inject_errors_mod);
                               inject_errors, inject_errors_mod, 0);
 
 
           end
           end
 
 
      end
      end
   endtask // do_rx_stim
   endtask // do_rx_stim
Line 286... Line 291...
                end
                end
 
 
              $display("do_rx_while_tx packet_size = %0d", packet_size);
              $display("do_rx_while_tx packet_size = %0d", packet_size);
              send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
              send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
                               IPG, 48'h0012_3456_789a,
                               IPG, 48'h0012_3456_789a,
                               48'h0708_090A_0B0C, 1, 1'b0, 0);
                               48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
 
 
              // If RX enable went low, wait for it go high again
              // If RX enable went low, wait for it go high again
              if (ethmac_rxen===1'b0)
              if (ethmac_rxen===1'b0)
                begin
                begin
 
 
Line 321... Line 326...
        if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
        if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
          // Continue if we are enabled
          // Continue if we are enabled
          do_rx_response_to_tx();
          do_rx_response_to_tx();
     end
     end
 
 
 
 
 
   // If in call-response mode, whenever we receive a TX packet, we generate
 
   // one and send it back
 
   always @(posedge eth_stim_do_overflow_test)
 
     begin
 
          // Continue if we are enabled
 
          do_overflow_stimulus();
 
     end
 
 
   // Generate RX packet in rsponse to TX packet
   // Generate RX packet in rsponse to TX packet
   task do_rx_response_to_tx;
   task do_rx_response_to_tx;
      //input unused;
      //input unused;
 
 
     reg [31:0] IPG; // Inter-packet gap
     reg [31:0] IPG; // Inter-packet gap
Line 356... Line 370...
           end
           end
 
 
         $display("do_rx_response_to_tx packet_size = %0d", packet_size);
         $display("do_rx_response_to_tx packet_size = %0d", packet_size);
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
                          IPG, 48'h0012_3456_789a,
                          IPG, 48'h0012_3456_789a,
                          48'h0708_090A_0B0C, 1, 1'b0, 0);
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
 
 
         // If RX enable went low, wait for it go high again
         // If RX enable went low, wait for it go high again
         if (ethmac_rxen===1'b0)
         if (ethmac_rxen===1'b0)
           begin
           begin
 
 
Line 377... Line 391...
           end
           end
 
 
      end
      end
   endtask // do_rx_response_to_tx
   endtask // do_rx_response_to_tx
 
 
 
   // Generate RX packet in rsponse to TX packet
 
   task do_overflow_stimulus;
 
      //input unused;
 
      reg [31:0] IPG; // Inter-packet gap
 
      reg [31:0] packet_size;
 
 
 
      integer    j;
 
 
 
      begin
 
 
 
         // Maximum packet size
 
         packet_size = 1500;
 
 
 
         // Minimum IPG
 
         IPG = eth_stim_IPG_min_100mb;
 
 
 
         $display("do_overflow_stimulus IPG = %0d", IPG);
 
 
 
 
 
         $display("do_overflow_stimulus packetsize = %0d", packet_size);
 
 
 
         send_packet_loop(num_rx_bds, packet_size, 2'b01, 1,
 
                          eth_phy0.eth_speed,
 
                          IPG, 48'h0012_3456_789a,
 
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
 
 
 
         // This one should cause overflow, don't check it gets there OK
 
         send_packet_loop(1, packet_size, 2'b01, 1,
 
                          eth_phy0.eth_speed,
 
                          IPG, 48'h0012_3456_789a,
 
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
 
 
 
         // Wind back expected RXBD number
 
         if (expected_rxbd == num_tx_bds)
 
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
 
         else
 
           expected_rxbd = expected_rxbd - 1;
 
 
 
         // This one should cause overflow, don't check it gets there OK
 
         send_packet_loop(1, packet_size, 2'b01, 1,
 
                          eth_phy0.eth_speed,
 
                          IPG, 48'h0012_3456_789a,
 
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
 
 
 
         // Wind back expected RXBD number
 
         if (expected_rxbd == num_tx_bds)
 
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
 
         else
 
           expected_rxbd = expected_rxbd - 1;
 
 
 
 
 
         // This one should cause overflow, don't check it gets there OK
 
         send_packet_loop(1, packet_size, 2'b01, 1,
 
                          eth_phy0.eth_speed,
 
                          IPG, 48'h0012_3456_789a,
 
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
 
 
 
         // Wind back expected RXBD number
 
         if (expected_rxbd == num_tx_bds)
 
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
 
         else
 
           expected_rxbd = expected_rxbd - 1;
 
 
 
 
 
         // This one should cause overflow, don't check it gets there OK
 
         send_packet_loop(1, packet_size, 2'b01, 1,
 
                          eth_phy0.eth_speed,
 
                          IPG, 48'h0012_3456_789a,
 
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 1);
 
 
 
         // Wind back expected RXBD number
 
         if (expected_rxbd == num_tx_bds)
 
           expected_rxbd = num_tx_bds + num_rx_bds - 1;
 
         else
 
           expected_rxbd = expected_rxbd - 1;
 
 
 
 
 
         // Wait until a buffer descriptor becomes available
 
         while(`ETH_TOP.wishbone.RxBDRead==1'b1)
 
           #1000;
 
 
 
         $display("%t: RxBDRead gone low",$time);
 
         #10000;
 
 
 
 
 
 
 
         send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
 
                          IPG, 48'h0012_3456_789a,
 
                          48'h0708_090A_0B0C, 1, 1'b0, 0, 0);
 
 
 
 
 
         // If RX enable went low, wait for it go high again
 
         if (ethmac_rxen===1'b0)
 
           begin
 
 
 
              while (ethmac_rxen===1'b0)
 
                begin
 
                   @(posedge ethmac_rxen);
 
                   #10000;
 
                end
 
 
 
              // RX disabled and when re-enabled we reset the buffer 
 
              // descriptor number
 
              expected_rxbd = num_tx_bds;
 
 
 
           end
 
 
 
      end
 
   endtask // do_overflow_stimulus
 
 
 
 
   //
   //
   // always@() to check the TX buffer descriptors
   // always@() to check the TX buffer descriptors
   //
   //
Line 651... Line 772...
         for (i=0;i<tx_len_bd;i=i+1)
         for (i=0;i<tx_len_bd;i=i+1)
           begin
           begin
              //$display("Checking address in tx bd 0x%0h",txpnt_sdram);
              //$display("Checking address in tx bd 0x%0h",txpnt_sdram);
              sdram_byte = 8'hx;
              sdram_byte = 8'hx;
`ifdef RAM_WB
`ifdef RAM_WB
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_mem8(txpnt_sdram);
`else
`else
 `ifdef VERSATILE_SDRAM
 `ifdef VERSATILE_SDRAM
              sdram0.get_byte(txpnt_sdram,sdram_byte);
              sdram0.get_byte(txpnt_sdram,sdram_byte);
 `else
 `else
  `ifdef XILINX_DDR2
  `ifdef XILINX_DDR2
Line 705... Line 826...
 
 
 
 
      end
      end
   endtask // check_tx_packet
   endtask // check_tx_packet
 
 
 
 
 
   // Local buffer of "sent" data to the ethernet MAC, we will check against
 
   // Size of our local buffer in bytes
 
   parameter eth_rx_sent_circbuf_size = (16*1024);
 
   parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1;
 
   integer eth_rx_sent_circbuf_fill_ptr = 0;
 
   integer eth_rx_sent_circbuf_read_ptr = 0;
 
   // The actual buffer
 
   reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1];
 
 
 
 
   //
   //
   // Task to send a set of packets
   // Task to send a set of packets
   //
   //
   task send_packet_loop;
   task send_packet_loop;
      input [31:0] num_packets;
      input [31:0] num_packets;
Line 720... Line 852...
      input [47:0] dst_mac;
      input [47:0] dst_mac;
      input [47:0] src_mac;
      input [47:0] src_mac;
      input        random_fill;
      input        random_fill;
      input        random_errors;
      input        random_errors;
      input [31:0] random_error_mod;
      input [31:0] random_error_mod;
      integer      j;
      input        dont_confirm_rx;
 
      integer      j, k;
      reg          error_this_time;
      reg          error_this_time;
      integer      error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO
      integer      error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO
      reg [31:0]   rx_bd_lenstat;
      reg [31:0]   rx_bd_lenstat;
      begin
      begin
         error_type = 0;
         error_type = 0;
Line 794... Line 927...
 
 
 
 
              // if RX enable still set (might have gone low during this packet
              // if RX enable still set (might have gone low during this packet
              if (ethmac_rxen)
              if (ethmac_rxen)
                begin
                begin
                   if (error_this_time)
                   if (error_this_time || dont_confirm_rx) begin
                     // Put in dummy length, checking function will skip...
                     // Put in dummy length, checking function will skip...
                     rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee;
                     rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee;
 
 
 
                      for(k=0;k<length;k=k+1)
 
                      // skip data  in verify buffer
 
                        eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
 
                                                       eth_rx_sent_circbuf_size_mask;
 
 
 
                   end
                   else
                   else
                     rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length;
                     rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length;
 
 
                   eth_rx_num_packets_sent = eth_rx_num_packets_sent + 1;
                   eth_rx_num_packets_sent = eth_rx_num_packets_sent + 1;
 
 
Line 848... Line 988...
 
 
           end // for (j=0;j<num_packets | length <32;j=j+1)
           end // for (j=0;j<num_packets | length <32;j=j+1)
      end
      end
   endtask // send_packet_loop
   endtask // send_packet_loop
 
 
   // Local buffer of "sent" data to the ethernet MAC, we will check against
 
   // Size of our local buffer in bytes
 
   parameter eth_rx_sent_circbuf_size = (16*1024);
 
   parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1;
 
   integer eth_rx_sent_circbuf_fill_ptr = 0;
 
   integer eth_rx_sent_circbuf_read_ptr = 0;
 
   // The actual buffer
 
   reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1];
 
 
 
   /*
   /*
    TASKS for set and check RX packets:
    TASKS for set and check RX packets:
    -----------------------------------
    -----------------------------------
    set_rx_packet
    set_rx_packet
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
Line 1174... Line 1305...
 
 
         for (i=0;i<len;i=i+1)
         for (i=0;i<len;i=i+1)
           begin
           begin
 
 
              sdram_byte = 8'hx;
              sdram_byte = 8'hx;
 
 
 
`ifdef RAM_WB
 
              sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_mem8(rxpnt_sdram);
 
`else
`ifdef XILINX_DDR2
`ifdef XILINX_DDR2
              get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
              get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
`else
`else
              $display(" * Error:");
              $display(" * Error:");
 
 
              $display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
              $display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
              $finish;
              $finish;
`endif
`endif
 
`endif
 
 
              phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
              phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
 
 
              if (phy_byte !== sdram_byte)
              if (phy_byte !== sdram_byte)
                begin
                begin

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