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/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
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/* ipc.h. Microkernel IPC header for Or1ksim
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Copyright (C) 2000 Damjan Lampret
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Copyright (C) 2008, 2010 Embecosm Limited
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Contributor Damjan Lampret <lampret@opencores.org>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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/* This file is part of test microkernel for OpenRISC 1000. */
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/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify it
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it under the terms of the GNU General Public License as published by
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under the terms of the GNU General Public License as published by the Free
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the Free Software Foundation; either version 2 of the License, or
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Software Foundation; either version 3 of the License, or (at your option)
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(at your option) any later version.
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any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful, but WITHOUT
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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GNU General Public License for more details.
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more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License along
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along with this program; if not, write to the Free Software
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This file is also used by microkernel test bench. Among
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/* This program is commented throughout in a fashion suitable for processing
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others it is also used in assembly file(s). */
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with Doxygen. */
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/* Definition of special-purpose registers (SPRs) */
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#ifndef __PORT_SPR_DEFS_H__
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#ifndef SPR_DEFS__H
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#define __PORT_SPR_DEFS_H__
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#define SPR_DEFS__H
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/* Definition of special-purpose registers (SPRs). */
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#define MAX_GRPS (32)
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#define MAX_GRPS (32)
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#define MAX_SPRS_PER_GRP_BITS (11)
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#define MAX_SPRS_PER_GRP_BITS (11)
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#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
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#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
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#define MAX_SPRS (0x10000)
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#define MAX_SPRS (0x10000)
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#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS)
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
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/* Data MMU group */
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/* Data MMU group */
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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Line 162... |
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/*
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/*
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* Bit definitions for the Version Register
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* Bit definitions for the Version Register
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*
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*
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*/
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*/
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_VER 0xff000000 /* Processor version */
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#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
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#define SPR_VR_RES 0x00ff0000 /* Reserved */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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#define SPR_VR_VER_OFF 24
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#define SPR_VR_CFG_OFF 16
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#define SPR_VR_REV_OFF 0
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/*
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/*
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* Bit definitions for the Unit Present Register
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* Bit definitions for the Unit Present Register
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*
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*
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*/
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*/
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#define SPR_UPR_UP 0x00000001 /* UPR present */
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#define SPR_UPR_UP 0x00000001 /* UPR present */
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#define SPR_UPR_DCP 0x00000002 /* Data cache present */
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#define SPR_UPR_DCP 0x00000002 /* Data cache present */
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#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
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#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
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#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
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#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
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#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
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#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
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#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */
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#define SPR_UPR_MP 0x00000020 /* MAC present */
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#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */
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#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
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#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */
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#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
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#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */
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#define SPR_UPR_PMP 0x00000100 /* Power management present */
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#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */
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#define SPR_UPR_PICP 0x00000200 /* PIC present */
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#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */
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#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
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#define SPR_UPR_DUP 0x00000800 /* Debug unit present */
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#define SPR_UPR_RES 0x00fe0000 /* Reserved */
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#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */
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#define SPR_UPR_CUP 0xff000000 /* Context units present */
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#define SPR_UPR_PMP 0x00002000 /* Power management present */
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#define SPR_UPR_PICP 0x00004000 /* PIC present */
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/*
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#define SPR_UPR_TTP 0x00008000 /* Tick timer present */
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* JPB: Bit definitions for the CPU configuration register
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#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */
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*
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#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */
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*/
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#define SPR_UPR_CUST 0xff000000 /* Custom units */
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#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
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#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
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#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
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#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
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#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
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#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
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#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
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#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
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/*
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* JPB: Bit definitions for the Debug configuration register and other
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* constants.
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*
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*/
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#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
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#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
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#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
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#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
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#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
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#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
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#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
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#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
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#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
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#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
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#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
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2 == n ? SPR_DCFGR_NDP2 : \
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3 == n ? SPR_DCFGR_NDP3 : \
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4 == n ? SPR_DCFGR_NDP4 : \
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5 == n ? SPR_DCFGR_NDP5 : \
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6 == n ? SPR_DCFGR_NDP6 : \
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7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
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#define MAX_MATCHPOINTS 8
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#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
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/*
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/*
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* Bit definitions for the Supervision Register
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* Bit definitions for the Supervision Register
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*
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*
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*/
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_CE 0x00000100 /* CID Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
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#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
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#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
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#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
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#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
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#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_CE 0x00000100 /* CID Enable */
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#define SPR_SR_F 0x00000200 /* Condition Flag */
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#define SPR_SR_CY 0x00000400 /* Carry flag */
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#define SPR_SR_OV 0x00000800 /* Overflow flag */
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#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
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#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
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#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
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#define SPR_SR_FO 0x00008000 /* Fixed one */
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#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
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#define SPR_SR_RES 0x0ffe0000 /* Reserved */
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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/*
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/*
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* Bit definitions for the Data MMU Control Register
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* Bit definitions for the Data MMU Control Register
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*
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*
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*/
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*/
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Line 279... |
*/
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*/
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
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#define SPR_DTLBMR_VPN 0xffffe000 /* Virtual Page Number */
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/*
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/*
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* Bit definitions for the Data TLB Translate Register
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* Bit definitions for the Data TLB Translate Register
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*
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*
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*/
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*/
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Line 295... |
#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_DTLBTR_PPN 0xffffe000 /* Physical Page Number */
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#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
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#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SWE )
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SPR_DTLBTR_SWE )
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/*
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/*
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* Bit definitions for the Instruction TLB Match Register
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* Bit definitions for the Instruction TLB Match Register
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*
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*
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*/
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*/
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
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#define SPR_ITLBMR_VPN 0xffffe000 /* Virtual Page Number */
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/*
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/*
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* Bit definitions for the Instruction TLB Translate Register
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* Bit definitions for the Instruction TLB Translate Register
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*
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*
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*/
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*/
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| Line 245... |
Line 324... |
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_ITLBTR_PPN 0xffffe000 /* Physical Page Number */
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#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
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#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
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SPR_ITLBTR_UXE )
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SPR_ITLBTR_UXE )
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/*
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/*
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* Bit definitions for Data Cache Control register
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* Bit definitions for Data Cache Control register
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*
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*
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*/
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*/
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#define SPR_DCCR_EW 0x000000ff /* Enable ways */
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#define SPR_DCCR_EW 0x000000ff /* Enable ways */
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| Line 263... |
Line 342... |
*
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*
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*/
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*/
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#define SPR_ICCR_EW 0x000000ff /* Enable ways */
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#define SPR_ICCR_EW 0x000000ff /* Enable ways */
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/*
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/*
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* Bit definitions for Data Cache Configuration Register
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*
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*/
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#define SPR_DCCFGR_NCW 0x00000007
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#define SPR_DCCFGR_NCS 0x00000078
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#define SPR_DCCFGR_CBS 0x00000080
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#define SPR_DCCFGR_CWS 0x00000100
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#define SPR_DCCFGR_CCRI 0x00000200
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#define SPR_DCCFGR_CBIRI 0x00000400
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#define SPR_DCCFGR_CBPRI 0x00000800
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#define SPR_DCCFGR_CBLRI 0x00001000
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#define SPR_DCCFGR_CBFRI 0x00002000
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#define SPR_DCCFGR_CBWBRI 0x00004000
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#define SPR_DCCFGR_NCW_OFF 0
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#define SPR_DCCFGR_NCS_OFF 3
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#define SPR_DCCFGR_CBS_OFF 7
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/*
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* Bit definitions for Instruction Cache Configuration Register
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*
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*/
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#define SPR_ICCFGR_NCW 0x00000007
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#define SPR_ICCFGR_NCS 0x00000078
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#define SPR_ICCFGR_CBS 0x00000080
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#define SPR_ICCFGR_CCRI 0x00000200
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#define SPR_ICCFGR_CBIRI 0x00000400
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#define SPR_ICCFGR_CBPRI 0x00000800
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#define SPR_ICCFGR_CBLRI 0x00001000
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#define SPR_ICCFGR_NCW_OFF 0
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#define SPR_ICCFGR_NCS_OFF 3
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#define SPR_ICCFGR_CBS_OFF 7
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/*
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* Bit definitions for Data MMU Configuration Register
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*
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*/
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#define SPR_DMMUCFGR_NTW 0x00000003
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#define SPR_DMMUCFGR_NTS 0x0000001C
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#define SPR_DMMUCFGR_NAE 0x000000E0
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#define SPR_DMMUCFGR_CRI 0x00000100
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#define SPR_DMMUCFGR_PRI 0x00000200
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#define SPR_DMMUCFGR_TEIRI 0x00000400
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#define SPR_DMMUCFGR_HTR 0x00000800
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#define SPR_DMMUCFGR_NTW_OFF 0
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#define SPR_DMMUCFGR_NTS_OFF 2
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/*
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* Bit definitions for Instruction MMU Configuration Register
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*
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*/
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#define SPR_IMMUCFGR_NTW 0x00000003
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#define SPR_IMMUCFGR_NTS 0x0000001C
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#define SPR_IMMUCFGR_NAE 0x000000E0
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#define SPR_IMMUCFGR_CRI 0x00000100
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#define SPR_IMMUCFGR_PRI 0x00000200
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#define SPR_IMMUCFGR_TEIRI 0x00000400
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#define SPR_IMMUCFGR_HTR 0x00000800
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#define SPR_IMMUCFGR_NTW_OFF 0
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#define SPR_IMMUCFGR_NTS_OFF 2
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/*
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* Bit definitions for Debug Control registers
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* Bit definitions for Debug Control registers
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*
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*
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*/
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*/
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_CC 0x0000000e /* Compare condition */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_SC 0x00000010 /* Signed compare */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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#define SPR_DCR_CT 0x000000e0 /* Compare to */
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/* Bit results with SPR_DCR_CC mask */
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/* Bit results with SPR_DCR_CC mask */
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_MASKED 0x00000000
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#define SPR_DCR_CC_EQUAL 0x00000001
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#define SPR_DCR_CC_EQUAL 0x00000002
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#define SPR_DCR_CC_LESS 0x00000002
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#define SPR_DCR_CC_LESS 0x00000004
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#define SPR_DCR_CC_LESSE 0x00000003
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#define SPR_DCR_CC_LESSE 0x00000006
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#define SPR_DCR_CC_GREAT 0x00000004
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#define SPR_DCR_CC_GREAT 0x00000008
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#define SPR_DCR_CC_GREATE 0x00000005
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#define SPR_DCR_CC_GREATE 0x0000000a
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#define SPR_DCR_CC_NEQUAL 0x00000006
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#define SPR_DCR_CC_NEQUAL 0x0000000c
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/* Bit results with SPR_DCR_CT mask */
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/* Bit results with SPR_DCR_CT mask */
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_DISABLED 0x00000000
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_IFEA 0x00000020
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_LEA 0x00000040
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_SEA 0x00000060
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_LD 0x00000080
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_SD 0x000000a0
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#define SPR_DCR_CT_LSEA 0x000000c0
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#define SPR_DCR_CT_LSEA 0x000000c0
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#define SPR_DCR_CT_LSD 0x000000e0
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/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
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/*
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/*
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* Bit definitions for Debug Mode 1 register
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* Bit definitions for Debug Mode 1 register
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*
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*
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*/
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*/
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#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */
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#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
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#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */
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#define SPR_DMR1_CW0_AND 0x00000001
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#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */
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#define SPR_DMR1_CW0_OR 0x00000002
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#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */
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#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
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#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */
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#define SPR_DMR1_CW1_AND 0x00000004
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#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */
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#define SPR_DMR1_CW1_OR 0x00000008
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#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */
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#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
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#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */
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#define SPR_DMR1_CW2_AND 0x00000010
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#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */
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#define SPR_DMR1_CW2_OR 0x00000020
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#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */
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#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
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#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */
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#define SPR_DMR1_CW3_AND 0x00000040
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#define SPR_DMR1_CW3_OR 0x00000080
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#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
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#define SPR_DMR1_CW4_AND 0x00000100
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#define SPR_DMR1_CW4_OR 0x00000200
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#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
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#define SPR_DMR1_CW5_AND 0x00000400
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#define SPR_DMR1_CW5_OR 0x00000800
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#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
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#define SPR_DMR1_CW6_AND 0x00001000
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#define SPR_DMR1_CW6_OR 0x00002000
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#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
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#define SPR_DMR1_CW7_AND 0x00004000
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#define SPR_DMR1_CW7_OR 0x00008000
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#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
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#define SPR_DMR1_CW8_AND 0x00010000
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#define SPR_DMR1_CW8_OR 0x00020000
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#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
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#define SPR_DMR1_CW9_AND 0x00040000
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#define SPR_DMR1_CW9_OR 0x00080000
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#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
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#define SPR_DMR1_RES1 0x00300000 /* Reserved */
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#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
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#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
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#define SPR_DMR1_BT 0x00800000 /* Branch trace */
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#define SPR_DMR1_BT 0x00800000 /* Branch trace */
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#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */
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#define SPR_DMR1_RES2 0xff000000 /* Reserved */
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/*
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/*
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* Bit definitions for Debug Mode 2 register
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* Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
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*
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*
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*/
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*/
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#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
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#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
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#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
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#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
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#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */
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#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
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#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */
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#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
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#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
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#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
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#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */
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#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
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/*
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/*
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* Bit definitions for Debug watchpoint counter registers
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* Bit definitions for Debug watchpoint counter registers
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*
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*
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*/
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*/
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#define SPR_DWCR_COUNT 0x0000ffff /* Count */
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#define SPR_DWCR_COUNT 0x0000ffff /* Count */
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#define SPR_DWCR_MATCH 0xffff0000 /* Match */
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#define SPR_DWCR_MATCH 0xffff0000 /* Match */
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#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
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/*
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/*
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* Bit definitions for Debug stop register
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* Bit definitions for Debug stop register
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*
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*
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*/
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*/
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| Line 340... |
Line 515... |
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
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#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
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#define SPR_DSR_TE 0x00002000 /* Trap exception */
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#define SPR_DSR_TE 0x00002000 /* Trap exception */
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/*
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/*
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* Bit definitions for Debug reason register
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* Bit definitions for Debug reason register
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*
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*
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| Line 359... |
Line 534... |
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_TE 0x00001000 /* Trap exception */
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#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
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#define SPR_DRR_TE 0x00002000 /* Trap exception */
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/*
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/*
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* Bit definitions for Performance counters mode registers
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* Bit definitions for Performance counters mode registers
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*
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*
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*/
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*/
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| Line 418... |
Line 594... |
*/
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*/
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_DI 0x00000000 /* Disabled */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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/*
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/*
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* Bit definitions for the FP Control Status Register
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*
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*/
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#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
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#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
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#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
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#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
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#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
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#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
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#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
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#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
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#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
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#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
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#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
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#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
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SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
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SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
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#define FPCSR_RM_RN (0<<1)
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#define FPCSR_RM_RZ (1<<1)
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#define FPCSR_RM_RIP (2<<1)
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#define FPCSR_RM_RIN (3<<1)
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/*
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* l.nop constants
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* l.nop constants
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*
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*
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*/
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*/
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_REPORT 0x0002 /* Simple report */
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#define NOP_REPORT 0x0002 /* Simple report */
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#define NOP_PRINTF 0x0003 /* Simprintf instruction */
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/*#define NOP_PRINTF 0x0003 Simprintf instruction (obsolete)*/
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#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */
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#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
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#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */
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#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */
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#define NOP_REPORT_FIRST 0x0400 /* Report with number */
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#define NOP_REPORT_FIRST 0x0400 /* Report with number */
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#define NOP_REPORT_LAST 0x03ff /* Report with number */
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#define NOP_REPORT_LAST 0x03ff /* Report with number */
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#endif // __PORT_SPR_DEFS_H__
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#endif /* SPR_DEFS__H */
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