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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 1163 and 1214

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Rev 1163	Rev 1214
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.12 2002/09/07 05:42:02 lampret`
	`// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.`
	`//`
`// Revision 1.11 2002/08/28 01:44:25 lampret`	`// Revision 1.11 2002/08/28 01:44:25 lampret`
`// Removed some commented RTL. Fixed SR/ESR flag bug.`	`// Removed some commented RTL. Fixed SR/ESR flag bug.`
`//`	`//`
`// Revision 1.10 2002/07/14 22:17:17 lampret`	`// Revision 1.10 2002/07/14 22:17:17 lampret`
`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`	`// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.`
Line 404...	Line 407...
`.epcr(epcr),`	`.epcr(epcr),`
`.spr_dat_i(spr_dat_cpu),`	`.spr_dat_i(spr_dat_cpu),`
`.spr_pc_we(pc_we),`	`.spr_pc_we(pc_we),`
`.genpc_refetch(genpc_refetch),`	`.genpc_refetch(genpc_refetch),`
`.genpc_freeze(genpc_freeze),`	`.genpc_freeze(genpc_freeze),`
	`.genpc_stop_prefetch(1'b0),`
`.no_more_dslot(no_more_dslot)`	`.no_more_dslot(no_more_dslot)`
`);`	`);`

`//`	`//`
`// Instantiation of instruction fetch block`	`// Instantiation of instruction fetch block`

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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Diff between revs 1163 and 1214