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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Diff between revs 504 and 1063

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Rev 504	Rev 1063
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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// OR1200's DC RAMs ////`	`//// OR1200's DC RAMs ////`
`//// ////`	`//// ////`
`//// This file is part of the OpenRISC 1200 project ////`	`//// This file is part of the OpenRISC 1200 project ////`
Line 42...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.8 2001/10/21 17:57:16 lampret`	`// Revision 1.8 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
`//`	`//`
`// Revision 1.7 2001/10/14 13:12:09 lampret`	`// Revision 1.7 2001/10/14 13:12:09 lampret`
`// MP3 version.`	`// MP3 version.`
Line 68...	Line 72...

`module or1200_dc_ram(`	`module or1200_dc_ram(`
`// Reset and clock`	`// Reset and clock`
`clk, rst,`	`clk, rst,`

	`ifdef OR1200_BIST
	`// RAM BIST`
	`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`
	`endif

`// Internal i/f`	`// Internal i/f`
`addr, en, we, datain, dataout`	`addr, en, we, datain, dataout`
`);`	`);`

parameter dw = `OR1200_OPERAND_WIDTH;	parameter dw = `OR1200_OPERAND_WIDTH;
Line 86...	Line 95...
`input en;`	`input en;`
`input [3:0] we;`	`input [3:0] we;`
`input [dw-1:0] datain;`	`input [dw-1:0] datain;`
`output [dw-1:0] dataout;`	`output [dw-1:0] dataout;`

	`ifdef OR1200_BIST
	`//`
	`// RAM BIST`
	`//`
	`input scanb_rst,`
	`scanb_si,`
	`scanb_en,`
	`scanb_clk;`
	`output scanb_so;`
	`endif

`ifdef OR1200_NO_DC	`ifdef OR1200_NO_DC

`//`	`//`
`// Data cache not implemented`	`// Data cache not implemented`
`//`	`//`

`assign dataout = {dw{1'b0}};`	`assign dataout = {dw{1'b0}};`
	`ifdef OR1200_BIST
	`assign scanb_so = scanb_si;`
	`endif

`else	`else

	`ifdef OR1200_BIST
	`//`
	`// RAM BIST`
	`//`
	`wire scanb_ram0_so;`
	`wire scanb_ram1_so;`
	`wire scanb_ram2_so;`
	`wire scanb_ram3_so;`
	`wire scanb_ram0_si = scanb_si;`
	`wire scanb_ram1_si = scanb_ram0_so;`
	`wire scanb_ram2_si = scanb_ram1_so;`
	`wire scanb_ram3_si = scanb_ram2_so;`
	`assign scanb_so = scanb_ram3_so;`
	`endif

`//`	`//`
`// Instantiation of RAM block 0`	`// Instantiation of RAM block 0`
`//`	`//`
`ifdef OR1200_DC_1W_4KB	`ifdef OR1200_DC_1W_4KB
`or1200_spram_1024x8 dc_ram0(`	`or1200_spram_1024x8 dc_ram0(`
`endif	`endif
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram0(`	`or1200_spram_2048x8 dc_ram0(`
`endif	`endif
	`ifdef OR1200_BIST
	`// RAM BIST`
	`.scanb_rst(scanb_rst),`
	`.scanb_si(scanb_ram0_si),`
	`.scanb_so(scanb_ram0_so),`
	`.scanb_en(scanb_en),`
	`.scanb_clk(scanb_clk),`
	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[0]),`	`.we(we[0]),`
`.oe(1'b1),`	`.oe(1'b1),`
Line 124...	Line 169...
`or1200_spram_1024x8 dc_ram1(`	`or1200_spram_1024x8 dc_ram1(`
`endif	`endif
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram1(`	`or1200_spram_2048x8 dc_ram1(`
`endif	`endif
	`ifdef OR1200_BIST
	`// RAM BIST`
	`.scanb_rst(scanb_rst),`
	`.scanb_si(scanb_ram1_si),`
	`.scanb_so(scanb_ram1_so),`
	`.scanb_en(scanb_en),`
	`.scanb_clk(scanb_clk),`
	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[1]),`	`.we(we[1]),`
`.oe(1'b1),`	`.oe(1'b1),`
Line 143...	Line 196...
`or1200_spram_1024x8 dc_ram2(`	`or1200_spram_1024x8 dc_ram2(`
`endif	`endif
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram2(`	`or1200_spram_2048x8 dc_ram2(`
`endif	`endif
	`ifdef OR1200_BIST
	`// RAM BIST`
	`.scanb_rst(scanb_rst),`
	`.scanb_si(scanb_ram2_si),`
	`.scanb_so(scanb_ram2_so),`
	`.scanb_en(scanb_en),`
	`.scanb_clk(scanb_clk),`
	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[2]),`	`.we(we[2]),`
`.oe(1'b1),`	`.oe(1'b1),`
Line 162...	Line 223...
`or1200_spram_1024x8 dc_ram3(`	`or1200_spram_1024x8 dc_ram3(`
`endif	`endif
`ifdef OR1200_DC_1W_8KB	`ifdef OR1200_DC_1W_8KB
`or1200_spram_2048x8 dc_ram3(`	`or1200_spram_2048x8 dc_ram3(`
`endif	`endif
	`ifdef OR1200_BIST
	`// RAM BIST`
	`.scanb_rst(scanb_rst),`
	`.scanb_si(scanb_ram3_si),`
	`.scanb_so(scanb_ram3_so),`
	`.scanb_en(scanb_en),`
	`.scanb_clk(scanb_clk),`
	`endif
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.ce(en),`	`.ce(en),`
`.we(we[3]),`	`.we(we[3]),`
`.oe(1'b1),`	`.oe(1'b1),`

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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Diff between revs 504 and 1063