| Line 60... |
Line 60... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
|
//
|
// Revision 1.8 2001/11/02 18:57:14 lampret
|
// Revision 1.8 2001/11/02 18:57:14 lampret
|
// Modified virtual silicon instantiations.
|
// Modified virtual silicon instantiations.
|
//
|
//
|
// Revision 1.7 2001/10/22 19:39:56 lampret
|
// Revision 1.7 2001/10/22 19:39:56 lampret
|
// Fixed parameters in generic sprams.
|
// Fixed parameters in generic sprams.
|
| Line 89... |
Line 92... |
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
module or1200_spram_64x24(
|
module or1200_spram_64x24(
|
|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
|
|
`endif
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
clk, rst, ce, we, oe, addr, di, do
|
clk, rst, ce, we, oe, addr, di, do
|
);
|
);
|
|
|
//
|
//
|
// Default address and data buses width
|
// Default address and data buses width
|
//
|
//
|
parameter aw = 6;
|
parameter aw = 6;
|
parameter dw = 24;
|
parameter dw = 24;
|
|
|
|
`ifdef OR1200_BIST
|
|
//
|
|
// RAM BIST
|
|
//
|
|
input scanb_rst,
|
|
scanb_si,
|
|
scanb_en,
|
|
scanb_clk;
|
|
output scanb_so;
|
|
`endif
|
|
|
//
|
//
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
//
|
//
|
input clk; // Clock
|
input clk; // Clock
|
input rst; // Reset
|
input rst; // Reset
|
| Line 116... |
Line 134... |
//
|
//
|
// Internal wires and registers
|
// Internal wires and registers
|
//
|
//
|
wire [7:0] unconnected;
|
wire [7:0] unconnected;
|
|
|
|
`ifdef OR1200_VIRTUALSILICON_SSP
|
|
`else
|
|
`ifdef OR1200_BIST
|
|
assign scanb_so = scanb_si;
|
|
`endif
|
|
`endif
|
|
|
`ifdef OR1200_ARTISAN_SSP
|
`ifdef OR1200_ARTISAN_SSP
|
|
|
//
|
//
|
// Instantiation of ASIC memory:
|
// Instantiation of ASIC memory:
|
//
|
//
|
| Line 189... |
Line 214... |
// Virtual Silicon Single-Port Synchronous SRAM
|
// Virtual Silicon Single-Port Synchronous SRAM
|
//
|
//
|
`ifdef UNUSED
|
`ifdef UNUSED
|
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
|
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
|
`else
|
`else
|
|
`ifdef OR1200_BIST
|
|
vs_hdsp_64x24_bist vs_ssp(
|
|
`else
|
vs_hdsp_64x24 vs_ssp(
|
vs_hdsp_64x24 vs_ssp(
|
`endif
|
`endif
|
|
`endif
|
|
`ifdef OR1200_BIST
|
|
// RAM BIST
|
|
.scanb_rst(scanb_rst),
|
|
.scanb_si(scanb_si),
|
|
.scanb_so(scanb_so),
|
|
.scanb_en(scanb_en),
|
|
.scanb_clk(scanb_clk),
|
|
`endif
|
.CK(clk),
|
.CK(clk),
|
.ADR(addr),
|
.ADR(addr),
|
.DI(di),
|
.DI(di),
|
.WEN(~we),
|
.WEN(~we),
|
.CEN(~ce),
|
.CEN(~ce),
|
