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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cpu/] [or1k/] [except.c] - Diff between revs 450 and 458

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Rev 450 Rev 458
Line 137... Line 137...
  if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
  if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
    if (config.sim.verbose)
    if (config.sim.verbose)
                  printf("INFO: Exception occured while exception detection was disabled.\n");
                  printf("INFO: Exception occured while exception detection was disabled.\n");
                return;
                return;
        }
        }
  pending.valid = 0;
 
  pending.type = 0;
 
  pending.address = 0;
 
  pending.saved = 0;
 
 
 
#if ONLY_VIRTUAL_MACHINE
#if ONLY_VIRTUAL_MACHINE
        fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
        fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
        cont_run = 0;
        cont_run = 0;
#else
#else
Line 161... Line 157...
                execute();
                execute();
        }
        }
#endif
#endif
 
 
        pc_saved = pc & ~0x3;
        pc_saved = pc & ~0x3;
 
  if (except == EXCEPT_ILLEGAL)
 
        mtspr(SPR_EPCR_BASE, pending.saved);
 
  else if (except == EXCEPT_ALIGN)
 
    mtspr(SPR_EPCR_BASE, pending.saved);
 
  else if (except == EXCEPT_DTLBMISS)
 
    mtspr(SPR_EPCR_BASE, pending.saved);
 
  else if (except == EXCEPT_DPF)
 
    mtspr(SPR_EPCR_BASE, pending.saved);
 
  else if (except == EXCEPT_BUSERR)
 
    mtspr(SPR_EPCR_BASE, pending.saved);
 
  else if (except == EXCEPT_TRAP)
 
    mtspr(SPR_EPCR_BASE, pending.saved);
 
  else if (except == EXCEPT_RANGE)
 
    mtspr(SPR_EPCR_BASE, pending.saved);
 
  else
        mtspr(SPR_EPCR_BASE, pc_saved);
        mtspr(SPR_EPCR_BASE, pc_saved);
 
 
        mtspr(SPR_EEAR_BASE, ea);
        mtspr(SPR_EEAR_BASE, ea);
        mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
        mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
 
 
        /* Address translation is always disabled when starting exception. */
        /* Address translation is always disabled when starting exception. */
        mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
        mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
        mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
        mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
 
 
 
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE);     /* Disable overflow flag exception. */
 
 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);     /* SUPV mode */
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);     /* SUPV mode */
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);     /* Disable interrupts. */
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);     /* Disable interrupts. */
 
 
 
  pending.valid = 0;
 
  pending.type = 0;
 
  pending.address = 0;
 
  pending.saved = 0;
 
 
        pc = (unsigned long)except;
        pc = (unsigned long)except;
 
 
        /* This has been removed. All exceptions (not just SYSCALL) suffer
        /* This has been removed. All exceptions (not just SYSCALL) suffer
           from the same problem. The solution is to continue just like
           from the same problem. The solution is to continue just like
           the pipeline would, and issue the exception on the next
           the pipeline would, and issue the exception on the next

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