Line 137... |
Line 137... |
if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
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if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
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if (config.sim.verbose)
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if (config.sim.verbose)
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printf("INFO: Exception occured while exception detection was disabled.\n");
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printf("INFO: Exception occured while exception detection was disabled.\n");
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return;
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return;
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}
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}
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pending.valid = 0;
|
|
pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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|
|
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#if ONLY_VIRTUAL_MACHINE
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#if ONLY_VIRTUAL_MACHINE
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fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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cont_run = 0;
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cont_run = 0;
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#else
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#else
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Line 161... |
Line 157... |
execute();
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execute();
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}
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}
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#endif
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#endif
|
|
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pc_saved = pc & ~0x3;
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pc_saved = pc & ~0x3;
|
|
if (except == EXCEPT_ILLEGAL)
|
|
mtspr(SPR_EPCR_BASE, pending.saved);
|
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else if (except == EXCEPT_ALIGN)
|
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_DTLBMISS)
|
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mtspr(SPR_EPCR_BASE, pending.saved);
|
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else if (except == EXCEPT_DPF)
|
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mtspr(SPR_EPCR_BASE, pending.saved);
|
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else if (except == EXCEPT_BUSERR)
|
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mtspr(SPR_EPCR_BASE, pending.saved);
|
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else if (except == EXCEPT_TRAP)
|
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mtspr(SPR_EPCR_BASE, pending.saved);
|
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else if (except == EXCEPT_RANGE)
|
|
mtspr(SPR_EPCR_BASE, pending.saved);
|
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else
|
mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EPCR_BASE, pc_saved);
|
|
|
mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
|
mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
|
|
|
/* Address translation is always disabled when starting exception. */
|
/* Address translation is always disabled when starting exception. */
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
|
|
|
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
|
|
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
|
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR); /* Disable interrupts. */
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR); /* Disable interrupts. */
|
|
|
|
pending.valid = 0;
|
|
pending.type = 0;
|
|
pending.address = 0;
|
|
pending.saved = 0;
|
|
|
pc = (unsigned long)except;
|
pc = (unsigned long)except;
|
|
|
/* This has been removed. All exceptions (not just SYSCALL) suffer
|
/* This has been removed. All exceptions (not just SYSCALL) suffer
|
from the same problem. The solution is to continue just like
|
from the same problem. The solution is to continue just like
|
the pipeline would, and issue the exception on the next
|
the pipeline would, and issue the exception on the next
|