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-- $Id: adder_09bit.vhdl,v 1.3 2005-03-04 08:06:11 arif_endro Exp $
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-- $Id: adder_09bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Adder 09 bit
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-- Title : Adder 09 bit
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-- Project : FM Receiver
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : adder_09bit.vhdl
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-- File : adder_09bit.vhdl
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Line 71... |
signal c06 : bit;
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signal c06 : bit;
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signal c07 : bit;
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signal c07 : bit;
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signal c08 : bit;
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signal c08 : bit;
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signal c09 : bit;
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signal c09 : bit;
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signal over09 : bit;
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signal over09 : bit;
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signal adder09_output_int : bit_vector (09 downto 0);
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signal adder09_output_int : bit_vector (08 downto 0);
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signal ov : bit ;
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begin
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begin
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c00 <= '0';
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c00 <= '0';
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over09 <= (addend_09bit (08) xor augend_09bit (08));
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over09 <= (addend_09bit (08) xor augend_09bit (08));
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adder09_output_int (09) <= ((adder09_output_int (08) and over09) or
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ov <= ((adder09_output_int (08) and over09) or
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(c09 and (not (over09))));
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(c09 and (not (over09))));
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adder09_output <= adder09_output_int;
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adder09_output(08 downto 00) <= adder09_output_int;
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adder09_output(09) <= ov;
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fa08 : fulladder
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fa08 : fulladder
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port map (
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port map (
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addend => addend_09bit(08),
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addend => addend_09bit(08),
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augend => augend_09bit(08),
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augend => augend_09bit(08),
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