| Line 1... |
Line 1... |
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TimeQuest Timing Analyzer Summary
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TimeQuest Timing Analyzer Summary
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Type : Slow 1100mV 85C Model Setup 'FPGA_CLK1_50'
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Type : Slow 1100mV 85C Model Setup 'FPGA_CLK1_50'
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Slack : 1.403
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Slack : 1.196
|
TNS : 0.000
|
TNS : 0.000
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Type : Slow 1100mV 85C Model Hold 'FPGA_CLK1_50'
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Type : Slow 1100mV 85C Model Hold 'FPGA_CLK1_50'
|
Slack : 0.221
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Slack : 0.271
|
TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 85C Model Recovery 'FPGA_CLK1_50'
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Type : Slow 1100mV 85C Model Recovery 'FPGA_CLK1_50'
|
Slack : 4.786
|
Slack : 4.785
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 85C Model Removal 'FPGA_CLK1_50'
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Type : Slow 1100mV 85C Model Removal 'FPGA_CLK1_50'
|
Slack : 0.870
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Slack : 0.979
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TNS : 0.000
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TNS : 0.000
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'din_a'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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Slack : 0.338
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Slack : 0.538
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TNS : 0.000
|
TNS : 0.000
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|
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'din_a'
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Slack : 0.364
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Slack : 0.597
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TNS : 0.000
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TNS : 0.000
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
|
Slack : 0.512
|
Slack : 0.657
|
TNS : 0.000
|
TNS : 0.000
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|
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
|
Slack : 0.537
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Slack : 0.679
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TNS : 0.000
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TNS : 0.000
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
|
Slack : 0.797
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Slack : 1.084
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Slack : 1.250
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Slack : 1.250
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TNS : 0.000
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TNS : 0.000
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| Line 45... |
Line 45... |
Type : Slow 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Type : Slow 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Slack : 4.202
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Slack : 4.202
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Setup 'FPGA_CLK1_50'
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Type : Slow 1100mV 0C Model Setup 'FPGA_CLK1_50'
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Slack : 1.581
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Slack : 1.204
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Hold 'FPGA_CLK1_50'
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Type : Slow 1100mV 0C Model Hold 'FPGA_CLK1_50'
|
Slack : 0.200
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Slack : 0.253
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TNS : 0.000
|
TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Recovery 'FPGA_CLK1_50'
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Type : Slow 1100mV 0C Model Recovery 'FPGA_CLK1_50'
|
Slack : 4.853
|
Slack : 4.852
|
TNS : 0.000
|
TNS : 0.000
|
|
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Type : Slow 1100mV 0C Model Removal 'FPGA_CLK1_50'
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Type : Slow 1100mV 0C Model Removal 'FPGA_CLK1_50'
|
Slack : 0.822
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Slack : 0.920
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'din_a'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
|
Slack : 0.332
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Slack : 0.465
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'din_a'
|
Slack : 0.364
|
Slack : 0.633
|
TNS : 0.000
|
TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Slack : 0.464
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Slack : 0.663
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TNS : 0.000
|
TNS : 0.000
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Slack : 0.580
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Slack : 0.716
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TNS : 0.000
|
TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
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Slack : 0.801
|
Slack : 1.117
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TNS : 0.000
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TNS : 0.000
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|
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Slack : 1.250
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Slack : 1.250
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TNS : 0.000
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TNS : 0.000
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| Line 89... |
Line 89... |
Type : Slow 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Type : Slow 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Slack : 4.284
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Slack : 4.284
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TNS : 0.000
|
TNS : 0.000
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Type : Fast 1100mV 85C Model Setup 'FPGA_CLK1_50'
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Type : Fast 1100mV 85C Model Setup 'FPGA_CLK1_50'
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Slack : 4.677
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Slack : 4.542
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Hold 'FPGA_CLK1_50'
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Type : Fast 1100mV 85C Model Hold 'FPGA_CLK1_50'
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Slack : 0.137
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Slack : 0.162
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Recovery 'FPGA_CLK1_50'
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Type : Fast 1100mV 85C Model Recovery 'FPGA_CLK1_50'
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Slack : 6.858
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Slack : 6.857
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Removal 'FPGA_CLK1_50'
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Type : Fast 1100mV 85C Model Removal 'FPGA_CLK1_50'
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Slack : 0.501
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Slack : 0.574
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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Slack : 0.364
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Slack : 0.799
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'din_a'
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'din_a'
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Slack : 0.497
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Slack : 0.812
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Slack : 0.759
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Slack : 0.897
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TNS : 0.000
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|
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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Slack : 0.799
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Slack : 1.029
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Slack : 0.920
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Slack : 1.250
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Slack : 1.250
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
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Slack : 1.333
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TNS : 0.000
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Type : Fast 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Slack : 4.076
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Slack : 4.076
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 0C Model Setup 'FPGA_CLK1_50'
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Type : Fast 1100mV 0C Model Setup 'FPGA_CLK1_50'
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Slack : 5.192
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Slack : 5.038
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 0C Model Hold 'FPGA_CLK1_50'
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Type : Fast 1100mV 0C Model Hold 'FPGA_CLK1_50'
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Slack : 0.122
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Slack : 0.146
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 0C Model Recovery 'FPGA_CLK1_50'
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Type : Fast 1100mV 0C Model Recovery 'FPGA_CLK1_50'
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Slack : 7.031
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Slack : 7.031
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 0C Model Removal 'FPGA_CLK1_50'
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Type : Fast 1100mV 0C Model Removal 'FPGA_CLK1_50'
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Slack : 0.453
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Slack : 0.524
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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Slack : 0.364
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Slack : 0.793
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TNS : 0.000
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TNS : 0.000
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'din_a'
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'din_a'
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Slack : 0.599
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Slack : 0.828
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TNS : 0.000
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
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|
Slack : 0.792
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TNS : 0.000
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TNS : 0.000
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|
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e'
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Slack : 0.860
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Slack : 0.961
|
TNS : 0.000
|
TNS : 0.000
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
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Slack : 1.057
|
Slack : 0.969
|
TNS : 0.000
|
TNS : 0.000
|
|
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
|
Slack : 1.250
|
Slack : 1.250
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TNS : 0.000
|
TNS : 0.000
|
|
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
|
|
Slack : 1.399
|
|
TNS : 0.000
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|
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
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Type : Fast 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
|
Slack : 4.039
|
Slack : 4.039
|
TNS : 0.000
|
TNS : 0.000
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