URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 14 |
Rev 16 |
| Line 38... |
Line 38... |
|
|
module sd_fifo_tail_b
|
module sd_fifo_tail_b
|
#(parameter width=8,
|
#(parameter width=8,
|
parameter depth=16,
|
parameter depth=16,
|
parameter commit=0,
|
parameter commit=0,
|
parameter asz=$clog2(depth))
|
parameter asz=$clog2(depth),
|
|
parameter usz=$clog2(depth+1)
|
|
)
|
(
|
(
|
input clk,
|
input clk,
|
input reset,
|
input reset,
|
input enable,
|
input enable,
|
|
|
| Line 53... |
Line 55... |
output reg [asz-1:0] com_rdptr,
|
output reg [asz-1:0] com_rdptr,
|
input [asz-1:0] wrptr,
|
input [asz-1:0] wrptr,
|
output reg mem_re,
|
output reg mem_re,
|
input mem_we,
|
input mem_we,
|
|
|
output reg [asz:0] usage,
|
output reg [usz:0] p_usage,
|
|
|
output p_srdy,
|
output p_srdy,
|
input p_drdy,
|
input p_drdy,
|
input p_commit,
|
input p_commit,
|
input p_abort,
|
input p_abort,
|
| Line 72... |
Line 74... |
reg nxt_irdy;
|
reg nxt_irdy;
|
|
|
reg [width-1:0] hold_a, hold_b;
|
reg [width-1:0] hold_a, hold_b;
|
reg valid_a, valid_b;
|
reg valid_a, valid_b;
|
reg prev_re;
|
reg prev_re;
|
reg [asz:0] tmp_usage;
|
reg [usz:0] tmp_usage;
|
reg [asz:0] fifo_size;
|
reg [usz:0] fifo_size;
|
wire rbuf1_drdy;
|
wire rbuf1_drdy;
|
wire ip_srdy, ip_drdy;
|
wire ip_srdy, ip_drdy;
|
wire [width-1:0] ip_data;
|
wire [width-1:0] ip_data;
|
|
|
// Stage 1 -- Read pipeline
|
// Stage 1 -- Read pipeline
|
| Line 116... |
Line 118... |
mem_re = 0;
|
mem_re = 0;
|
end // else: !if(enable & !empty & (!valid_a | !valid_b |...
|
end // else: !if(enable & !empty & (!valid_a | !valid_b |...
|
|
|
fifo_size = (bound_high - bound_low + 1);
|
fifo_size = (bound_high - bound_low + 1);
|
tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
|
tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
|
if (~tmp_usage[asz])
|
if (~tmp_usage[usz])
|
usage = tmp_usage[asz-1:0];
|
p_usage = tmp_usage[usz-1:0];
|
else
|
else
|
usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
|
p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
|
end // always @ *
|
end // always @ *
|
|
|
/* -----\/----- EXCLUDED -----\/-----
|
/* -----\/----- EXCLUDED -----\/-----
|
// alternate usage calc
|
// alternate usage calc
|
reg [asz-1:0] prev_wr;
|
reg [asz-1:0] prev_wr;
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.