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//
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//
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// Xilinx VHDL ROM generator
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// Xilinx VHDL ROM generator
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//
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//
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// Version : 0241
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// Version : 0244
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//
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//
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// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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//
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//
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// All rights reserved
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// All rights reserved
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//
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//
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// 0220 : Initial release
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// 0220 : Initial release
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//
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//
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// 0221 : Fixed block ROMs with partial bytes
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// 0221 : Fixed block ROMs with partial bytes
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//
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//
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// 0241 : Updated for WebPack 5.1
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// 0241 : Updated for WebPack 5.1
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//
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// 0244 : Added -n option and component declaration
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <string>
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#include <string>
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#include <vector>
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#include <vector>
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#include <iostream>
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#include <iostream>
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#define max __max
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#define max __max
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#endif
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#endif
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int main (int argc, char *argv[])
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int main (int argc, char *argv[])
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{
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{
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cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0241\n";
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cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0244\n";
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try
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try
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{
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{
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unsigned long aWidth;
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unsigned long aWidth;
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unsigned long dWidth;
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unsigned long dWidth;
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unsigned long select = 0;
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unsigned long select = 0;
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unsigned long length = 0;
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char z = 0;
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char z = 0;
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if (argc < 4)
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if (argc < 4)
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{
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{
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cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
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cerr << "\nUsage: xrom <entity name> <address bits> <data bits> <options>\n";
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cerr << "\nThe options can be:\n";
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cerr << "\nThe options can be:\n";
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cerr << " -[decimal number] = SelectRAM usage in 1/16 parts\n";
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cerr << " -[decimal number] = SelectRAM usage in 1/16 parts\n";
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cerr << " -z = use tri-state buses\n";
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cerr << " -z = use tri-state buses\n";
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cerr << " -n [decimal size] = limit rom size\n";
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cerr << "\nExample:\n";
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cerr << "\nExample:\n";
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cerr << " xrom Test_ROM 13 8 -6\n\n";
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cerr << " xrom Test_ROM 13 8 -6\n\n";
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return -1;
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return -1;
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}
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}
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if (result < 1)
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if (result < 1)
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{
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{
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throw "Error in data bits argument!\n";
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throw "Error in data bits argument!\n";
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}
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}
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if (argc > 4)
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int argument = 4;
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while (argument < argc)
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{
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{
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result = sscanf(argv[4], "%c%lu", &z, &select);
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char tmpC = 0;
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if (result < 1 || z != '-')
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unsigned long tmpL = 0;
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result = sscanf(argv[argument], "%c%lu", &tmpC, &tmpL);
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if (result < 1 || tmpC != '-' )
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{
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{
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throw "Error in options!\n";
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throw "Error in options!\n";
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}
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}
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if (result < 2)
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if (result < 2)
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{
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{
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sscanf(argv[4], "%c%c", &z, &z);
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sscanf(argv[argument], "%c%c", &tmpC, &tmpC);
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if (z != 'z')
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if (tmpC != 'z' && tmpC != 'n')
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{
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{
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throw "Error in options!\n";
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throw "Unkown option!\n";
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}
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}
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}
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if (tmpC == 'z')
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{
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z = tmpC;
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}
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}
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else
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if (argc > 5)
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{
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{
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result = sscanf(argv[5], "%c%lu", &z, &select);
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argument++;
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if (result < 1 || z != '-')
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if (argument == argc)
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{
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{
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throw "Error in options!\n";
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throw "No memory size argument!\n";
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}
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}
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if (result < 2)
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{
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result = sscanf(argv[argument], "%lu", &tmpL);
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sscanf(argv[5], "%c%c", &z, &z);
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if (!result)
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if (z != 'z')
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{
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{
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throw "Error in options!\n";
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throw "Memory size not a number!\n";
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}
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}
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length = tmpL;
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}
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}
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}
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}
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else
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{
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select = tmpL;
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}
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argument++;
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}
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unsigned long selectIter = 0;
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unsigned long selectIter = 0;
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unsigned long blockIter = 0;
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unsigned long blockIter = 0;
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unsigned long bytes = (dWidth + 7) / 8;
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unsigned long bytes = (dWidth + 7) / 8;
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if (!select)
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if (!select)
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{
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{
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blockIter = ((1UL << aWidth) + 511) / 512;
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blockIter = ((1UL << aWidth) + 511) / 512;
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if (length && length < blockIter * 512)
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{
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blockIter = (length + 511) / 512;
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}
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}
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}
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else if (select == 16)
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else if (select == 16)
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{
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{
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selectIter = ((1UL << aWidth) + 15) / 16;
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selectIter = ((1UL << aWidth) + 15) / 16;
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if (length && length < selectIter * 16)
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{
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selectIter = (length + 15) / 16;
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}
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}
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}
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else
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else
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{
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{
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blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
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blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
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selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
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selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
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}
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}
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unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
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unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
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if (length && length < blockTotal * 512)
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{
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blockTotal = (length + 511) / 512;
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}
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if (length)
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{
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if (length > selectIter * 16)
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{
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blockIter -= ((1UL << aWidth) + 511) / 512 - blockTotal;
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}
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else
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{
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blockIter = 0;
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}
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}
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if (length && !blockIter && length < selectIter * 16)
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{
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selectIter = (length + 15) / 16;
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}
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cerr << "Creating ROM with " << selectIter * bytes;
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cerr << " RAM16X1S and " << blockIter * bytes << " RAMB4_S8\n";
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printf("-- This file was generated with xrom written by Daniel Wallner\n");
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printf("-- This file was generated with xrom written by Daniel Wallner\n");
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printf("\nlibrary IEEE;");
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printf("\nlibrary IEEE;");
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printf("\nuse IEEE.std_logic_1164.all;");
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printf("\nuse IEEE.std_logic_1164.all;");
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printf("\nuse IEEE.numeric_std.all;");
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printf("\nuse IEEE.numeric_std.all;");
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printf("\nlibrary UNISIM;");
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printf("\nuse UNISIM.vcomponents.all;");
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printf("\n\nentity %s is", argv[1]);
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printf("\n\nentity %s is", argv[1]);
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printf("\n\tport(");
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printf("\n\tport(");
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printf("\n\t\tClk\t: in std_logic;");
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printf("\n\t\tClk\t: in std_logic;");
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printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
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printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
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printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
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printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
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printf("\n\t);");
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printf("\n\t);");
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printf("\nend %s;", argv[1]);
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printf("\nend %s;", argv[1]);
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printf("\n\narchitecture rtl of %s is", argv[1]);
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printf("\n\narchitecture rtl of %s is", argv[1]);
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if (selectIter)
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{
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printf("\n\tcomponent RAM16X1S");
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printf("\n\t\tport(");
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printf("\n\t\t\tO : out std_ulogic;");
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printf("\n\t\t\tA0 : in std_ulogic;");
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printf("\n\t\t\tA1 : in std_ulogic;");
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printf("\n\t\t\tA2 : in std_ulogic;");
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printf("\n\t\t\tA3 : in std_ulogic;");
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printf("\n\t\t\tD : in std_ulogic;");
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printf("\n\t\t\tWCLK : in std_ulogic;");
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printf("\n\t\t\tWE : in std_ulogic);");
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printf("\n\tend component;\n");
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}
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if (blockIter)
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{
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printf("\n\tcomponent RAMB4_S8");
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printf("\n\t\tport(");
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printf("\n\t\t\tDO : out std_logic_vector(7 downto 0);");
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printf("\n\t\t\tADDR : in std_logic_vector(8 downto 0);");
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printf("\n\t\t\tCLK : in std_ulogic;");
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printf("\n\t\t\tDI : in std_logic_vector(7 downto 0);");
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printf("\n\t\t\tEN : in std_ulogic;");
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printf("\n\t\t\tRST : in std_ulogic;");
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printf("\n\t\t\tWE : in std_ulogic);");
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printf("\n\tend component;\n");
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}
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if (selectIter > 0)
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if (selectIter > 0)
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{
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{
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printf("\n\tsignal A_r: unsigned(A'range);");
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printf("\n\tsignal A_r: unsigned(A'range);");
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}
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}
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if (selectIter > 1)
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if (selectIter > 1)
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Line 298... |
}
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}
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if (selectIter == 1)
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if (selectIter == 1)
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{
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{
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printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
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printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
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printf("\n\t\tS%s : LUT4\n\t\t\tport map (", argv[1]);
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printf("\n\t\tS%s : RAM16X1S\n\t\t\tport map (", argv[1]);
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if (blockIter)
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if (blockIter)
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{
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{
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printf("s");
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printf("s");
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}
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}
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printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");
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printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");
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