URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1200r2/] [or1200_ctrl.v] - Diff between revs 18 and 48

Rev 18	Rev 48
Line 144...	Line 144...
`//`	`//`
`input clk;`	`input clk;`
`input rst;`	`input rst;`
`input id_freeze;`	`input id_freeze;`
`input ex_freeze;`	`input ex_freeze;`
`input wb_freeze;`	`input wb_freeze /* verilator public */;`
`input flushpipe;`	`input flushpipe;`
`input [31:0] if_insn;`	`input [31:0] if_insn;`
`output [31:0] ex_insn;`	`output [31:0] ex_insn;`
output [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;	output [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;	output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
Line 267...	Line 267...
`//`	`//`
`//`	`//`
`//`	`//`
assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) \| (branch_op == `OR1200_BRANCHOP_RFE);	assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) \| (branch_op == `OR1200_BRANCHOP_RFE);

	`ifdef verilator
	`// Function to access wb_insn (for Verilator). Have to hide this from`
	`// simulator, since functions with no inputs are not allowed in IEEE`
	`// 1364-2001.`
	`function [31:0] get_wb_insn;`
	`// verilator public`
	`get_wb_insn = wb_insn;`
	`endfunction // get_wb_insn`
	`endif


`//`	`//`
`// Generation of sel_a`	`// Generation of sel_a`
`//`	`//`
`always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`	`always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)`
`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`	`if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])`