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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [smii/] [generic_buffers.v] - Diff between revs 18 and 22

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Rev 18 Rev 22
Line 77... Line 77... 
   output o,
 
   output o,
 
   inout pad
 
   inout pad
 
   );
 
   );
 
 
 
 
 
   assign #1 pad = oe ? i : 1'bz;
 
   assign #1 pad = oe ? i : 1'bz;
 
   assign #1 i = pad;
 
   assign #1 o = pad;
 
 
 
 
 
endmodule // iobuftri
 
endmodule // iobuftri
 
 
 
 
 
module obuf
 
module obuf
 
  (
 
  (

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