| Line 102... |
Line 102... |
mdio_out,
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mdio_out,
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|
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// configuration output
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// configuration output
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cf_mac_sa,
|
cf_mac_sa,
|
cfg_ip_sa,
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cfg_ip_sa,
|
cfg_mac_filter
|
cfg_mac_filter,
|
|
rx_buf_base_addr,
|
|
tx_buf_base_addr,
|
|
|
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rx_buf_qbase_addr,
|
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tx_buf_qbase_addr,
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|
|
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tx_qcnt_inc,
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tx_qcnt_dec,
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tx_qcnt,
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|
|
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rx_qcnt_inc,
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rx_qcnt_dec,
|
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rx_qcnt
|
|
|
);
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);
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|
|
parameter mac_mdio_en = 1'b1;
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parameter mac_mdio_en = 1'b1;
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| Line 189... |
Line 202... |
output mdio_out;
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output mdio_out;
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|
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output [47:0] cf_mac_sa;
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output [47:0] cf_mac_sa;
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output [31:0] cfg_ip_sa;
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output [31:0] cfg_ip_sa;
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output [31:0] cfg_mac_filter;
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output [31:0] cfg_mac_filter;
|
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output [3:0] rx_buf_base_addr;
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output [3:0] tx_buf_base_addr;
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|
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output [9:0] rx_buf_qbase_addr; // Rx Q Base Address
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output [9:0] tx_buf_qbase_addr; // Tx Q Base Address
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|
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input tx_qcnt_inc;
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input tx_qcnt_dec;
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output [3:0] tx_qcnt;
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|
|
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input rx_qcnt_inc;
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input rx_qcnt_dec;
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output [3:0] rx_qcnt;
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|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// RX-Clock Domain Status Signal
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// RX-Clock Domain Status Signal
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//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
wire rx_sts_vld_o;
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wire rx_sts_vld_o;
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wire [15:0] rx_sts_bytes_rcvd_o;
|
wire [15:0] rx_sts_bytes_rcvd_o;
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| Line 515... |
Line 542... |
//MDIO CONTROL & DATA
|
//MDIO CONTROL & DATA
|
.cf2md_datain (cf2md_datain),
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.cf2md_datain (cf2md_datain),
|
.cf2md_regad (cf2md_regad),
|
.cf2md_regad (cf2md_regad),
|
.cf2md_phyad (cf2md_phyad),
|
.cf2md_phyad (cf2md_phyad),
|
.cf2md_op (cf2md_op),
|
.cf2md_op (cf2md_op),
|
.cf2md_go (cf2md_go)
|
.cf2md_go (cf2md_go),
|
|
|
|
.rx_buf_base_addr (rx_buf_base_addr),
|
|
.tx_buf_base_addr (tx_buf_base_addr),
|
|
|
|
.rx_buf_qbase_addr (rx_buf_qbase_addr),
|
|
.tx_buf_qbase_addr (tx_buf_qbase_addr),
|
|
|
|
.tx_qcnt_inc (tx_qcnt_inc),
|
|
.tx_qcnt_dec (tx_qcnt_dec),
|
|
.tx_qcnt (tx_qcnt),
|
|
|
|
.rx_qcnt_inc (rx_qcnt_inc),
|
|
.rx_qcnt_dec (rx_qcnt_dec),
|
|
.rx_qcnt (rx_qcnt)
|
|
|
|
|
);
|
);
|
|
|
g_mii_intf u_mii_intf(
|
g_mii_intf u_mii_intf(
|
// Data and Control Signals to tx_fsm and rx_fsm
|
// Data and Control Signals to tx_fsm and rx_fsm
|
.mi2rx_strt_rcv (mi2rx_strt_rcv),
|
.mi2rx_strt_rcv (mi2rx_strt_rcv),
|
