| Line 70... |
Line 70... |
rx2ap_rx_fsm_dt,
|
rx2ap_rx_fsm_dt,
|
// Fifo Control Signal to Fifo Management Block
|
// Fifo Control Signal to Fifo Management Block
|
rx2ap_commit_write,
|
rx2ap_commit_write,
|
rx2ap_rewind_write,
|
rx2ap_rewind_write,
|
// To address filtering block
|
// To address filtering block
|
// Pause control to Tx block
|
|
rx2tx_pause_tx,
|
|
//commit
|
//commit
|
commit_write_done,
|
commit_write_done,
|
|
|
// Global Signals
|
// Global Signals
|
reset_n,
|
reset_n,
|
| Line 91... |
Line 89... |
// Rx fifo management signal to indicate overrun
|
// Rx fifo management signal to indicate overrun
|
rx_fifo_full,
|
rx_fifo_full,
|
ap2rx_rx_fifo_err,
|
ap2rx_rx_fifo_err,
|
// Signal from CRC check block
|
// Signal from CRC check block
|
rc2rx_crc_ok,
|
rc2rx_crc_ok,
|
// Signals from Address filtering block
|
|
af2rx_pause_frame,
|
|
// Signals from Config Management Block
|
// Signals from Config Management Block
|
cf2rx_max_pkt_sz,
|
cf2rx_max_pkt_sz,
|
cf2rx_rx_ch_en,
|
cf2rx_rx_ch_en,
|
cf2rx_strp_pad_en,
|
cf2rx_strp_pad_en,
|
cf2rx_snd_crc,
|
cf2rx_snd_crc,
|
cf2rx_pause_en,
|
|
cf2rx_rcv_runt_pkt_en,
|
cf2rx_rcv_runt_pkt_en,
|
cf2rx_gigabit_xfr,
|
cf2rx_gigabit_xfr,
|
//A200 change Port added for crs based flow control
|
//A200 change Port added for crs based flow control
|
phy_crs,
|
phy_crs
|
//A200 change crs flow control enable signal
|
|
crs_flow_control_enable,
|
|
//A200 change pause detected pulse for counter
|
|
pause_frame_detected
|
|
|
|
);
|
);
|
|
|
|
|
parameter MIN_FRM_SIZE = 6'h2e ;
|
parameter MIN_FRM_SIZE = 6'h2e ;
|
| Line 133... |
Line 124... |
// has to be sent to application
|
// has to be sent to application
|
output rx2ap_rewind_write; // This indicates the previous packet
|
output rx2ap_rewind_write; // This indicates the previous packet
|
// in the FIFO has a error
|
// in the FIFO has a error
|
// Ignore the packet and restart from the
|
// Ignore the packet and restart from the
|
// end of previous packet
|
// end of previous packet
|
output rx2tx_pause_tx; // pause frame detected pause transmit
|
|
output clr_rx_error_from_rx_fsm;
|
output clr_rx_error_from_rx_fsm;
|
output commit_write_done;
|
output commit_write_done;
|
|
|
output pause_frame_detected; //A200 change bringing out a pulse to count number
|
|
//pause frames received.
|
|
|
|
input reset_n; // reset from mac application interface
|
input reset_n; // reset from mac application interface
|
input phy_rx_clk; // Reference clock used for RX
|
input phy_rx_clk; // Reference clock used for RX
|
|
|
input mi2rx_strt_rcv; // Receive data from the PHY
|
input mi2rx_strt_rcv; // Receive data from the PHY
|
input mi2rx_rcv_vld; // Received nibble is valid
|
input mi2rx_rcv_vld; // Received nibble is valid
|
| Line 158... |
Line 145... |
// RX FIFO MGMT block
|
// RX FIFO MGMT block
|
|
|
input rc2rx_crc_ok; // CRC of the receiving packet is OK.
|
input rc2rx_crc_ok; // CRC of the receiving packet is OK.
|
// Generated by CRC block
|
// Generated by CRC block
|
|
|
input af2rx_pause_frame; // Detected a pause frame
|
|
|
|
input [15:0] cf2rx_max_pkt_sz; // max packet size
|
input [15:0] cf2rx_max_pkt_sz; // max packet size
|
|
|
input cf2rx_rx_ch_en; // Receive Enabled
|
input cf2rx_rx_ch_en; // Receive Enabled
|
input cf2rx_strp_pad_en; // Do not Append padding after the data
|
input cf2rx_strp_pad_en; // Do not Append padding after the data
|
input cf2rx_snd_crc; // Append CRC to the data
|
input cf2rx_snd_crc; // Append CRC to the data
|
// ( This automatically means padding
|
// ( This automatically means padding
|
// will be enabled)
|
// will be enabled)
|
input cf2rx_pause_en; // This is set when flow control is enabled
|
|
input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
|
input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
|
input cf2rx_gigabit_xfr;
|
input cf2rx_gigabit_xfr;
|
input mi2rx_extend;
|
input mi2rx_extend;
|
|
|
//A200 change Port added for crs based flow control
|
//A200 change Port added for crs based flow control
|
input phy_crs;
|
input phy_crs;
|
//A200 change crs flow control enable signal
|
|
input crs_flow_control_enable;
|
|
|
|
|
|
/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
|
/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
|
reg rx2ap_commit_write;
|
reg rx2ap_commit_write;
|
reg rx2ap_rewind_write;
|
reg rx2ap_rewind_write;
|
reg [8:0] rx2ap_rx_fsm_dt;
|
reg [8:0] rx2ap_rx_fsm_dt;
|
reg rx2ap_rx_fsm_wrt;
|
reg rx2ap_rx_fsm_wrt;
|
wire [31:0] rx_sts_dt;
|
wire [31:0] rx_sts_dt;
|
reg [31:0] rx_sts;
|
reg [31:0] rx_sts;
|
wire rx2tx_pause_tx;
|
|
//Renamed to rx2tx_pause_tx_int as rx2tx_pause_tx is genrated in CRS
|
|
//condition also
|
|
reg rx2tx_pause_tx_int;
|
|
|
|
/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
|
/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
|
reg commit_write;
|
reg commit_write;
|
reg rewind_write;
|
reg rewind_write;
|
wire pause_dn;
|
|
wire look_at_length_field;
|
wire look_at_length_field;
|
reg send_crc;
|
reg send_crc;
|
reg rcv_pad_data;
|
reg rcv_pad_data;
|
reg first_dword;
|
reg first_dword;
|
wire [15:0] inc_rcv_byte_count;
|
wire [15:0] inc_rcv_byte_count;
|
| Line 217... |
Line 194... |
reg error;
|
reg error;
|
reg error_seen;
|
reg error_seen;
|
reg commit_write_done;
|
reg commit_write_done;
|
reg check_padding;
|
reg check_padding;
|
reg check_padding_in;
|
reg check_padding_in;
|
reg gen_pause_det;
|
|
reg pause_opcode_detected;
|
|
reg ld_pause_quanta_1,ld_pause_quanta_2;
|
|
reg [2:0] padding_len_reg;
|
reg [2:0] padding_len_reg;
|
reg [15:0] rcv_length_reg;
|
reg [15:0] rcv_length_reg;
|
reg [15:0] length_counter;
|
reg [15:0] length_counter;
|
|
|
reg [18:0] rx_fsm_cur_st;
|
reg [18:0] rx_fsm_cur_st;
|
reg [18:0] rx_fsm_nxt_st;
|
reg [18:0] rx_fsm_nxt_st;
|
reg [15:0] pause_quanta;
|
|
reg [1:0] c_pause_ptr;
|
|
reg [15:0] pause_count;
|
|
reg [8:0] pause_quanta_count;
|
|
reg crc_stat_reg;
|
reg crc_stat_reg;
|
reg rx_runt_pkt_reg;
|
reg rx_runt_pkt_reg;
|
reg large_pkt_reg;
|
reg large_pkt_reg;
|
reg rx_fifo_overrun_reg;
|
reg rx_fifo_overrun_reg;
|
reg frm_length_err_reg;
|
reg frm_length_err_reg;
|
| Line 245... |
Line 215... |
reg [2:0] bytes_to_fifo;
|
reg [2:0] bytes_to_fifo;
|
reg [7:0] buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
|
reg [7:0] buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
|
wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
|
wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
|
reg lengthfield_error;
|
reg lengthfield_error;
|
reg lengthfield_err_reg;
|
reg lengthfield_err_reg;
|
reg pause_frame_detected;
|
|
reg pause_seen;
|
|
reg addr_stat_chk;
|
reg addr_stat_chk;
|
reg clr_rx_error_from_rx_fsm;
|
reg clr_rx_error_from_rx_fsm;
|
|
|
wire [15:0] adj_rcv_length_reg;
|
wire [15:0] adj_rcv_length_reg;
|
wire [15:0] adj_rcv_byte_count;
|
wire [15:0] adj_rcv_byte_count;
|
| Line 264... |
Line 232... |
rx_fsm_lk4len_byte2_st = 19'b0000000000000001000,
|
rx_fsm_lk4len_byte2_st = 19'b0000000000000001000,
|
rx_fsm_getdt_nib1_st = 19'b0000000000000010000,
|
rx_fsm_getdt_nib1_st = 19'b0000000000000010000,
|
rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
|
rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
|
rx_fsm_updstat_st = 19'b0000000000001000000,
|
rx_fsm_updstat_st = 19'b0000000000001000000,
|
rx_fsm_chkval_st = 19'b0000000000010000000,
|
rx_fsm_chkval_st = 19'b0000000000010000000,
|
rx_fsm_pausectrl_st = 19'b0000000000100000000,
|
rx_fsm_extend_st = 19'b0000000100000000000;
|
rx_fsm_extend_st = 19'b0000000100000000000,
|
|
rx_fsm_pausequanta_byte1_st = 19'b0000001000000000000,
|
|
rx_fsm_pausequanta_byte2_st = 19'b0000010000000000000,
|
|
rx_fsm_wt4_pause_end_st = 19'b0000100000000000000;
|
|
|
|
/***************** WIRE ASSIGNMENTS *************************/
|
/***************** WIRE ASSIGNMENTS *************************/
|
wire [6:0] dec_pad_length;
|
wire [6:0] dec_pad_length;
|
wire [15:0] inc_length_counter;
|
wire [15:0] inc_length_counter;
|
wire rx_overrun_error;
|
wire rx_overrun_error;
|
| Line 351... |
Line 315... |
|
|
// configured max packet size should be 16'd1518.
|
// configured max packet size should be 16'd1518.
|
assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
|
assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
|
|
|
|
|
always @(posedge phy_rx_clk or negedge reset_n) begin
|
|
if(!reset_n)
|
|
pause_opcode_detected <= 1'b0;
|
|
else
|
|
begin
|
|
if(rx_fsm_cur_st == rx_fsm_pausequanta_byte1_st)
|
|
pause_opcode_detected <= 1'b1;
|
|
else if(rx_fsm_cur_st == rx_fsm_idle_st)
|
|
pause_opcode_detected <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// Following state machine is to receive nibbles from the RMII/MII
|
// Following state machine is to receive nibbles from the RMII/MII
|
// block and packetize them to 32 bits with information of EOP and
|
// block and packetize them to 32 bits with information of EOP and
|
// valid bytes. It also discards packets which are less than minimum
|
// valid bytes. It also discards packets which are less than minimum
|
// frame size. It performs Address validity and Data validity.
|
// frame size. It performs Address validity and Data validity.
|
always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
|
always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
|
or cf2rx_snd_crc or cf2rx_pause_en or look_at_length_field
|
or cf2rx_snd_crc or look_at_length_field
|
or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
|
or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
|
or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
|
or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
|
or inc_length_counter or rcv_length_reg or commit_write_done
|
or inc_length_counter or rcv_length_reg or commit_write_done
|
or crc_count or shift_counter or bytes_to_fifo
|
or crc_count or shift_counter or bytes_to_fifo
|
or af2rx_pause_frame or cf2rx_rcv_runt_pkt_en
|
or cf2rx_rcv_runt_pkt_en
|
or inc_rcv_byte_count or send_runt_packet
|
or inc_rcv_byte_count or send_runt_packet
|
or pause_frame_detected or rcv_byte_count or first_dword
|
or rcv_byte_count or first_dword
|
or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
|
or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
|
//or pause_opcode_detected)
|
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_cur_st;
|
rx_fsm_nxt_st = rx_fsm_cur_st;
|
set_tag1_flag = 1'b0;
|
set_tag1_flag = 1'b0;
|
set_tag2_flag = 1'b0;
|
set_tag2_flag = 1'b0;
|
reset_tmp_count = 1'b0;
|
reset_tmp_count = 1'b0;
|
| Line 398... |
Line 350... |
set_incomplete_frm = 1'b0;
|
set_incomplete_frm = 1'b0;
|
set_frm_lngth_error = 1'b0;
|
set_frm_lngth_error = 1'b0;
|
gen_eop = 1'b0;
|
gen_eop = 1'b0;
|
error = 1'b0;
|
error = 1'b0;
|
byte_boundary= 1'b0;
|
byte_boundary= 1'b0;
|
gen_pause_det = 1'b0;
|
|
ld_pause_quanta_1 = 1'b0;
|
|
ld_pause_quanta_2 = 1'b0;
|
|
send_crc = 1'b0;
|
send_crc = 1'b0;
|
rcv_pad_data = 1'b0;
|
rcv_pad_data = 1'b0;
|
inc_shift_counter = 1'b0;
|
inc_shift_counter = 1'b0;
|
send_data_to_fifo = 1'b0;
|
send_data_to_fifo = 1'b0;
|
lengthfield_error = 1'b0;
|
lengthfield_error = 1'b0;
|
pause_seen = 1'b0;
|
|
addr_stat_chk = 1'b0;
|
addr_stat_chk = 1'b0;
|
clr_rx_error_from_rx_fsm = 1'b0;
|
clr_rx_error_from_rx_fsm = 1'b0;
|
//pause_opcode_detected = 1'b0;
|
|
|
|
|
|
casex(rx_fsm_cur_st) // synopsys parallel_case full_case
|
casex(rx_fsm_cur_st) // synopsys parallel_case full_case
|
rx_fsm_idle_st:
|
rx_fsm_idle_st:
|
// Waiting for packet from mii block
|
// Waiting for packet from mii block
|
// Continues accepting data only if
|
// Continues accepting data only if
|
// receive has been enabled
|
// receive has been enabled
|
begin
|
begin
|
//pause_opcode_detected = 1'b0;
|
|
if(ap2rx_rx_fifo_err)
|
if(ap2rx_rx_fifo_err)
|
begin
|
begin
|
clr_rx_error_from_rx_fsm = 1'b1;
|
clr_rx_error_from_rx_fsm = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
| Line 458... |
Line 404... |
end
|
end
|
end // if (mi2rx_end_rcv)
|
end // if (mi2rx_end_rcv)
|
|
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
|
begin
|
begin
|
if(cf2rx_pause_en && af2rx_pause_frame)
|
|
begin
|
|
pause_seen = 1;
|
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
|
rewind_write = 1'b1;
|
|
end
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
|
| Line 499... |
Line 438... |
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
end
|
end
|
end
|
end
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
|
begin
|
begin
|
if(pause_frame_detected)
|
|
rx_fsm_nxt_st = rx_fsm_pausectrl_st;
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
| Line 786... |
Line 722... |
begin
|
begin
|
e_rx_sts_vld = 1'b1;
|
e_rx_sts_vld = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
|
|
rx_fsm_pausectrl_st:
|
|
// collecting odd nibbles of pause control
|
|
// in case of termination of packet
|
|
// or carrier sense error then generate eop
|
|
// and generate status
|
|
begin
|
|
if(mi2rx_end_rcv)
|
|
begin
|
|
set_incomplete_frm = 1'b1;
|
|
error = 1'b1;
|
|
gen_eop = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
|
if(cf2rx_rcv_runt_pkt_en)
|
|
commit_write = 1'b1;
|
|
else
|
|
rewind_write = 1'b1;
|
|
end
|
|
else if(mi2rx_rcv_vld)
|
|
case(inc_rcv_byte_count[1:0])
|
|
2'b01 : if(mi2rx_rx_byte != 8'h88)
|
|
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
|
|
2'b10 : if(mi2rx_rx_byte != 8'h08)
|
|
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
|
|
2'b11 : if(mi2rx_rx_byte != 8'h00)
|
|
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
|
|
2'b00 : begin
|
|
if(mi2rx_rx_byte != 8'h01)
|
|
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_pausequanta_byte1_st;
|
|
end
|
|
endcase
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_pausectrl_st;
|
|
end // case: rx_fsm_pausectrl_nib1_st
|
|
|
|
rx_fsm_pausequanta_byte1_st:
|
|
// This state collects the odd nibbles of the receive data
|
|
begin
|
|
//pause_opcode_detected = 1'b1;
|
|
if(ap2rx_rx_fifo_err)
|
|
begin
|
|
rewind_write = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
|
end
|
|
else if(mi2rx_end_rcv)
|
|
begin
|
|
set_incomplete_frm = 1'b1;
|
|
error = 1'b1;
|
|
gen_eop = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
|
if(cf2rx_rcv_runt_pkt_en)
|
|
commit_write = 1'b1;
|
|
else
|
|
rewind_write = 1'b1;
|
|
end
|
|
else if(mi2rx_rcv_vld)
|
|
begin
|
|
ld_pause_quanta_1 = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_pausequanta_byte2_st;
|
|
end
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_pausequanta_byte1_st;
|
|
end // case: rx_fsm_pausequanta_nib1_st
|
|
|
|
rx_fsm_pausequanta_byte2_st:
|
|
// This state collects the even nibbles of the receive data.
|
|
begin
|
|
//pause_opcode_detected = 1'b1;
|
|
if(ap2rx_rx_fifo_err)
|
|
begin
|
|
rewind_write = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
|
end
|
|
else if(mi2rx_end_rcv)
|
|
begin
|
|
set_incomplete_frm = 1'b1;
|
|
error = 1'b1;
|
|
gen_eop = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
|
end
|
|
else if(mi2rx_rcv_vld )
|
|
begin
|
|
ld_pause_quanta_2 = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
|
|
end
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_pausequanta_byte2_st;
|
|
end // case: rx_fsm_pausequanta_nib2_st
|
|
|
|
rx_fsm_wt4_pause_end_st:
|
|
begin
|
|
//pause_opcode_detected = 1'b1;
|
|
if(ap2rx_rx_fifo_err)
|
|
begin
|
|
rewind_write = 1'b1;
|
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
|
end
|
|
else if(mi2rx_end_rcv)
|
|
begin
|
|
if(rcv_byte_count[14:0] < 15'd64) // mfilardo
|
|
begin
|
|
lengthfield_error = 1;
|
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
|
end
|
|
else if(rc2rx_crc_ok)
|
|
begin
|
|
gen_pause_det = 1;
|
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
|
end
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
|
end
|
|
else
|
|
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
|
|
end // case: rx_fsm_wt4_pause_end_st
|
|
default:
|
default:
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
endcase // casex(rx_fsm_cur_st)
|
endcase // casex(rx_fsm_cur_st)
|
| Line 961... |
Line 781... |
assign look_at_length_field = cf2rx_strp_pad_en &&
|
assign look_at_length_field = cf2rx_strp_pad_en &&
|
(rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
|
(rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
|
assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
|
assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
|
(rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
|
(rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
|
|
|
//
|
|
// Detect pause control frame
|
|
always @(posedge phy_rx_clk
|
|
or negedge reset_n)
|
|
begin
|
|
if(!reset_n)
|
|
pause_frame_detected <= 1'b0;
|
|
else if(mi2rx_end_rcv)
|
|
pause_frame_detected <= 1'b0;
|
|
else if(af2rx_pause_frame && cf2rx_pause_en && pause_seen)
|
|
pause_frame_detected <= 1'b1;
|
|
end // always @ (posedge phy_rx_clk...
|
|
|
|
// counter used for decrementing pause to transmit
|
|
always @(posedge phy_rx_clk
|
|
or negedge reset_n)
|
|
begin
|
|
if(!reset_n)
|
|
pause_count <= 16'b0;
|
|
else
|
|
begin
|
|
if(~cf2rx_pause_en)
|
|
pause_count <= 'h0;
|
|
else if(gen_pause_det & pause_opcode_detected)
|
|
pause_count <= pause_quanta;
|
|
//else if(pause_quanta_count == 9'd511)
|
|
else if( ( cf2rx_gigabit_xfr && (pause_quanta_count[5:0] == 6'd63 )) ||
|
|
(~cf2rx_gigabit_xfr && (pause_quanta_count[6:0] == 7'd127)) ) // mfilardo pause bit time fix. A pause quanta should be 512 bit times.
|
|
pause_count <= pause_count - 1;
|
|
end // else: !if(!reset_n)
|
|
end // always @ (posedge phy_rx_clk...
|
|
|
|
// counter used for decrementing pause quanta count
|
|
// which is 512 bit times
|
|
always @(posedge phy_rx_clk
|
|
or negedge reset_n)
|
|
begin
|
|
if(!reset_n)
|
|
pause_quanta_count <= 9'b0;
|
|
else
|
|
begin
|
|
if(pause_dn)
|
|
pause_quanta_count <= 9'b0;
|
|
else if(rx2tx_pause_tx_int)
|
|
pause_quanta_count <= pause_quanta_count + 1;
|
|
end // else: !if(!reset_n)
|
|
end
|
|
|
|
assign pause_dn = ~|pause_count & rx2tx_pause_tx_int;
|
|
//A200 change :
|
|
//When phy_crs input is asserted rx2tx_pause_tx which stops the
|
|
//frame transmission. Same function has been done on receiving pause
|
|
//frame so phy_crs is ored with pause receive signal when config is
|
|
//zero.
|
|
assign rx2tx_pause_tx = rx2tx_pause_tx_int |
|
|
(phy_crs & ~crs_flow_control_enable);
|
|
|
|
// Generation pause to tx_fsm
|
|
always @(posedge phy_rx_clk
|
|
or negedge reset_n)
|
|
begin
|
|
if(!reset_n)
|
|
rx2tx_pause_tx_int <= 1'b0;
|
|
else
|
|
begin
|
|
if(pause_dn)
|
|
rx2tx_pause_tx_int <= 1'b0;
|
|
else if(gen_pause_det)
|
|
rx2tx_pause_tx_int <= 1'b1;
|
|
end // else: !if(!reset_n)
|
|
end // always @ (posedge phy_rx_clk...
|
|
|
|
assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
|
assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
| Line 1352... |
Line 1103... |
end // else: !if(mi2rx_strt_rcv)
|
end // else: !if(mi2rx_strt_rcv)
|
end // if (rx_ch_en)
|
end // if (rx_ch_en)
|
end // else: !if(!reset_n)
|
end // else: !if(!reset_n)
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
// This is used load the pause quanta value on received
|
|
// pause control frame
|
|
always @(posedge phy_rx_clk or negedge reset_n)
|
|
begin
|
|
if(!reset_n)
|
|
begin
|
|
pause_quanta <= 16'b0;
|
|
c_pause_ptr <= 2'b0;
|
|
end // if (reset_n)
|
|
else if (rx_ch_en)
|
|
begin
|
|
if(mi2rx_strt_rcv)
|
|
begin
|
|
pause_quanta <= 16'b0;
|
|
c_pause_ptr <= 2'b0;
|
|
end
|
|
else
|
|
begin
|
|
if(ld_pause_quanta_1)
|
|
begin
|
|
pause_quanta[15:8] <= mi2rx_rx_byte;
|
|
end
|
|
else if(ld_pause_quanta_2)
|
|
begin
|
|
pause_quanta[7:0] <= mi2rx_rx_byte;
|
|
end
|
|
end // else: !if(mi2rx_strt_rcv)
|
|
end // else: !if(!reset_n)
|
|
end
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
