URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testSerial_transmitter.vhd] - Diff between revs 36 and 37
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 36 |
Rev 37 |
| Line 11... |
Line 11... |
ARCHITECTURE behavior OF testSerial_transmitter IS
|
ARCHITECTURE behavior OF testSerial_transmitter IS
|
|
|
-- Component Declaration for the Unit Under Test (UUT)
|
-- Component Declaration for the Unit Under Test (UUT)
|
|
|
COMPONENT serial_transmitter
|
COMPONENT serial_transmitter
|
PORT(
|
Port ( rst : in STD_LOGIC; --! Reset input
|
rst : IN std_logic;
|
baudClk : in STD_LOGIC; --! Baud rate clock input
|
baudClk : IN std_logic;
|
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
|
data_byte : IN std_logic_vector(7 downto 0);
|
data_sent : out STD_LOGIC; --! Indicate that byte has been sent
|
data_sent : OUT std_logic;
|
serial_out : out STD_LOGIC); --! Uart serial output
|
serial_out : OUT std_logic
|
|
);
|
|
END COMPONENT;
|
END COMPONENT;
|
|
|
|
|
--Inputs
|
--Inputs
|
signal rst : std_logic := '0';
|
signal rst : std_logic := '0'; --! Signal to connect with UUT
|
signal baudClk : std_logic := '0';
|
signal baudClk : std_logic := '0'; --! Signal to connect with UUT
|
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
|
signal data_byte : std_logic_vector(7 downto 0) := (others => '0'); --! Signal to connect with UUT
|
|
|
--Outputs
|
--Outputs
|
signal data_sent : std_logic;
|
signal data_sent : std_logic; --! Signal to connect with UUT
|
signal serial_out : std_logic;
|
signal serial_out : std_logic; --! Signal to connect with UUT
|
|
|
-- Clock period definitions
|
-- Clock period definitions
|
constant baudClk_period : time := 10 ns;
|
constant baudClk_period : time := 10 ns;
|
|
|
BEGIN
|
BEGIN
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.