| Line 7... |
Line 7... |
// Purpose: This file isn't really a part of the synthesis implementation
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// Purpose: This file isn't really a part of the synthesis implementation
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// of the wb2axip project itself, but rather it is an example
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// of the wb2axip project itself, but rather it is an example
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// of how the wb2axip project can be used to connect a MIG generated
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// of how the wb2axip project can be used to connect a MIG generated
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// IP component.
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// IP component.
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//
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//
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// This implementation depends upon the existence of a MIG generated
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// core, named "mig_axis", and illustrates how such a core might be
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// connected to the wbm2axip bridge. Specific options of the mig_axis
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// setup include 6 identifier bits, and a full-sized bus width of 128
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// bits. These two settings are both appropriate for driving a DDR3
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// memory (whose minimum transfer size is 128 bits), but may need to be
|
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// adjusted to support other memories.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 26... |
Line 33... |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
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`default_nettype none
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//
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module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset,
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module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset,
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// Wishbone components
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// Wishbone components
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
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o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
|
// SDRAM connections
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// SDRAM connections
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| Line 69... |
Line 78... |
:((WBDATAWIDTH==64) ? RAMABITS-3
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:((WBDATAWIDTH==64) ? RAMABITS-3
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:((WBDATAWIDTH==128) ? RAMABITS-4
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:((WBDATAWIDTH==128) ? RAMABITS-4
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: RAMABITS-5)); // (WBDATAWIDTH==256)
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: RAMABITS-5)); // (WBDATAWIDTH==256)
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localparam SELW= (WBDATAWIDTH/8);
|
localparam SELW= (WBDATAWIDTH/8);
|
//
|
//
|
input i_clk, i_clk_200mhz, i_rst;
|
input wire i_clk, i_clk_200mhz, i_rst;
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output o_sys_clk;
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output wire o_sys_clk;
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output reg o_sys_reset;
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output reg o_sys_reset;
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//
|
//
|
input i_wb_cyc, i_wb_stb, i_wb_we;
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input [(AW-1):0] i_wb_addr;
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input wire [(AW-1):0] i_wb_addr;
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input [(DW-1):0] i_wb_data;
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input wire [(DW-1):0] i_wb_data;
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input [(SELW-1):0] i_wb_sel;
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input wire [(SELW-1):0] i_wb_sel;
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output wire o_wb_ack, o_wb_stall;
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output wire o_wb_ack, o_wb_stall;
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output wire [(DW-1):0] o_wb_data;
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output wire [(DW-1):0] o_wb_data;
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output wire o_wb_err;
|
output wire o_wb_err;
|
//
|
//
|
output wire [0:0] o_ddr_ck_p, o_ddr_ck_n;
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output wire [0:0] o_ddr_ck_p, o_ddr_ck_n;
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| Line 133... |
Line 142... |
wire [0:0] s_axi_arlock;
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wire [0:0] s_axi_arlock;
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wire [3:0] s_axi_arcache;
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wire [3:0] s_axi_arcache;
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wire [2:0] s_axi_arprot;
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wire [2:0] s_axi_arprot;
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wire [3:0] s_axi_arqos;
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wire [3:0] s_axi_arqos;
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wire s_axi_arvalid;
|
wire s_axi_arvalid;
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|
wire s_axi_arready;
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// Read response/data channel
|
// Read response/data channel
|
wire [(AXIDWIDTH-1):0] s_axi_rid;
|
wire [(AXIDWIDTH-1):0] s_axi_rid;
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wire [(AXIWIDTH-1):0] s_axi_rdata;
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wire [(AXIWIDTH-1):0] s_axi_rdata;
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wire [1:0] s_axi_rresp;
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wire [1:0] s_axi_rresp;
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wire s_axi_rlast;
|
wire s_axi_rlast;
|
wire s_axi_rvalid;
|
wire s_axi_rvalid;
|
|
wire s_axi_rready;
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|
|
// Other wires ...
|
// Other wires ...
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wire init_calib_complete, mmcm_locked;
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wire init_calib_complete, mmcm_locked;
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wire app_sr_active, app_ref_ack, app_zq_ack;
|
wire app_sr_active, app_ref_ack, app_zq_ack;
|
wire app_sr_req, app_ref_req, app_zq_req;
|
wire app_sr_req, app_ref_req, app_zq_req;
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