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module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter SINGLE_CYCLE = 1'b0, //
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parameter SINGLE_CYCLE = 1'b0, //
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parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
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parameter DWIDTH = 16) // Data bus width
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parameter DWIDTH = 16) // Data bus width
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(
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(
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// Wishbone Signals
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// Wishbone Slave Signals
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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// Wishbone Master Signals
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output [DWIDTH-1:0] wbm_dat_o, // databus output
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output wbm_we_o, // write enable output
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output wbm_stb_o, // stobe/core select signal
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output wbm_cyc_o, // valid bus cycle output
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output [ 1:0] wbm_sel_o, // Select byte in word bus transaction
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output [15:0] wbm_adr_o, // Address bits
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input wbm_ack_i, // bus cycle acknowledge input
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// XGATE IO Signals
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// XGATE IO Signals
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output [ 7:0] xgswt, // XGATE Software Trigger Register
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output [ 7:0] xgswt, // XGATE Software Trigger Register
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output [15:0] xgate_address,
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output write_mem_strb_l, // Strobe for writing low data byte
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output write_mem_strb_l, // Strobe for writing low data byte
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output write_mem_strb_h, // Strobe for writing high data bye
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output write_mem_strb_h, // Strobe for writing high data bye
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output [15:0] write_mem_data,
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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input [15:0] read_mem_data,
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input risc_clk, // Clock for RISC core
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input risc_clk, // Clock for RISC core
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input scantestmode // Chip in in scan test mode
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input scantestmode // Chip in in scan test mode
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);
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);
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wire zero_flag;
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wire zero_flag;
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wire negative_flag;
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wire negative_flag;
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wire carry_flag;
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wire carry_flag;
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wire overflow_flag;
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wire overflow_flag;
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wire [15:0] xgr1; // XGATE Register #1
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wire [15:0] xgr1; // XGATE Register #1
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wire xgie; // XGATE Interrupt Enable
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wire xgie; // XGATE Interrupt Enable
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [15:1] xgvbr; // XGATE vector Base Address Register
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wire [15:1] xgvbr; // XGATE vector Base Address Register
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wire [ 2:0] semaph_risc; // Semaphore register select from RISC
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wire [15:0] xgate_address; //
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wire [15:0] write_mem_data; //
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wire [15:0] read_mem_data; //
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wire mem_req_ack; //
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wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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// wire [15:0] write_mem_data;
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// wire [15:0] write_mem_data;
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// wire [15:0] read_mem_data;
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// wire [15:0] read_mem_data;
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// wire [15:0] perif_data;
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// wire [15:0] perif_data;
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// inputs
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// inputs
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.risc_clk( risc_clk ),
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.risc_clk( risc_clk ),
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.perif_data( wbs_dat_i ),
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.perif_data( wbs_dat_i ),
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.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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.read_mem_data( read_mem_data ),
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.read_mem_data( read_mem_data ),
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.mem_req_ack( mem_req_ack ),
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.xge( xge ),
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.xge( xge ),
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.xgfrz( xgfrz ),
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.xgfrz( xgfrz ),
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.xgdbg( xgdbg ),
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.xgdbg( xgdbg ),
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.xgss( xgss ),
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.xgss( xgss ),
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.xgvbr( xgvbr ),
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.xgvbr( xgvbr ),
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.int_req( int_req ),
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.int_req( int_req ),
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// inputs
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// inputs
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.chan_req_i( chan_req_i )
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.chan_req_i( chan_req_i )
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);
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);
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// ---------------------------------------------------------------------------
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// Wishbone Master Bus interface
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xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
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wishbone_m(
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// Wishbone Master Signals
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.wbm_dat_o( wbm_dat_o ),
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.wbm_we_o( wbm_we_o ),
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.wbm_stb_o( wbm_stb_o ),
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.wbm_cyc_o( wbm_cyc_o ),
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.wbm_sel_o( wbm_sel_o ),
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.wbm_adr_o( wbm_adr_o ),
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.wbm_dat_i( wbm_dat_i ),
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.wbm_ack_i( wbm_ack_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_rst_i( wbs_rst_i ),
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.arst_i( arst_i ),
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// XGATE Control Signals
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.read_mem_data( read_mem_data ),
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.xgate_address( xgate_address ),
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.mem_req_ack( mem_req_ack ),
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.write_mem_strb_l( write_mem_strb_l ),
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.write_mem_strb_h( write_mem_strb_h ),
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.write_mem_data( write_mem_data )
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);
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endmodule // xgate_top
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endmodule // xgate_top
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