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# Global
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# Global
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# ------
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# ------
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set script_dir [file dirname [file normalize [info script]]]
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set script_dir [file dirname [file normalize [info script]]]
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# Name
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# Name
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set ::env(DESIGN_NAME) scr1_top_axi
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set ::env(DESIGN_NAME) scr1_top_wb
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# This is macro
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# This is macro
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set ::env(DESIGN_IS_CORE) 0
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set ::env(DESIGN_IS_CORE) 0
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# Diode insertion
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# Diode insertion
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# Sources
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# Sources
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# -------
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# -------
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# Local sources + no2usb sources
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# Local sources + no2usb sources
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set ::env(VERILOG_FILES) "\
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set ::env(VERILOG_FILES) "\
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv \
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$script_dir/../../verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv "
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv \
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$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv \
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$script_dir/../../verilog/rtl/lib/sync_fifo.sv "
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set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore_scr1/src/includes ]
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set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
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#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
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#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
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# Need blackbox for cells
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# Need blackbox for cells
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