| Line 292... |
Line 292... |
//
|
//
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
(~master_ce)
|
(~master_ce)
|
// Stall waiting for flags to be valid
|
// Stall waiting for flags to be valid
|
||((~opF[8])&&(
|
|
((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))
|
|
// Do I need this last condition?
|
|
||(wr_flags_ce)))
|
|
// Or waiting for a write to the PC register
|
// Or waiting for a write to the PC register
|
// Or CC register, since that can change the
|
// Or CC register, since that can change the
|
// PC as well
|
// PC as well
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
|
|
| Line 569... |
Line 565... |
// use that value.
|
// use that value.
|
opA_rd <= dcdA_rd;
|
opA_rd <= dcdA_rd;
|
opB_rd <= dcdB_rd;
|
opB_rd <= dcdB_rd;
|
op_pc <= dcd_pc;
|
op_pc <= dcd_pc;
|
//
|
//
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc));
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
|
end
|
end
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
|
|
// This is tricky. First, the PC and Flags registers aren't kept in
|
// This is tricky. First, the PC and Flags registers aren't kept in
|
// register set but in special registers of their own. So step one
|
// register set but in special registers of their own. So step one
|
| Line 597... |
Line 593... |
`else
|
`else
|
assign opA = r_opA;
|
assign opA = r_opA;
|
`endif
|
`endif
|
|
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
|
`define DONT_STALL_ON_OPB
|
`define DONT_STALL_ON_OPA
|
`ifdef DONT_STALL_ON_OPB
|
`ifdef DONT_STALL_ON_OPA
|
// Skip the requirement on writing back opA
|
// Skip the requirement on writing back opA
|
// Stall on memory, since we'll always need to stall for a
|
// Stall on memory, since we'll always need to stall for a
|
// memory access anyway
|
// memory access anyway
|
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
|
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
|
|
((opvalid_alu)&&(opF_wr)&&(dcdA_cc))||
|
`else
|
`else
|
((opvalid)&&(opR_wr)&&(opR == dcdA))||
|
((opvalid)&&(opR_wr)&&(opR == dcdA))||
|
`endif
|
`endif
|
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
|
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
|
|
`define DONT_STALL_ON_OPB
|
`ifdef DONT_STALL_ON_OPB
|
`ifdef DONT_STALL_ON_OPB
|
reg opB_alu;
|
reg opB_alu;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
|
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
|
| Line 618... |
Line 616... |
`else
|
`else
|
assign opB = r_opB;
|
assign opB = r_opB;
|
`endif
|
`endif
|
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
|
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
|
((opvalid)&&(opR_wr)&&(opR == dcdB)
|
((opvalid)&&(opR_wr)&&(opR == dcdB)
|
|
&&((opvalid_mem)||(dcdI != 0)))
|
|
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
|
`ifdef DONT_STALL_ON_OPB
|
`ifdef DONT_STALL_ON_OPB
|
&&((opvalid_mem)||(dcdI != 0))
|
|
`endif
|
`endif
|
)||
|
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
|
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
|
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
|
assign dcdF_stall = (dcdvalid)&&(
|
&&(opvalid)&&(opR_cc);
|
(((~dcdF[3]) ||(dcdA_cc) ||(dcdB_cc))
|
|
&&(opvalid)&&((opR_cc)||(opF_wr)))
|
|
||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #4 :: Apply Instruction
|
// PIPELINE STAGE #4 :: Apply Instruction
|
//
|
//
|
//
|
//
|
