/*
|
/*
|
* MC6809 specific processing
|
* MC6809 specific processing
|
*/
|
*/
|
|
|
#define PAGE2 0x10
|
#define PAGE2 0x10
|
#define PAGE3 0x11
|
#define PAGE3 0x11
|
#define IPBYTE 0x9F /* extended indirect postbyte */
|
#define IPBYTE 0x9F /* extended indirect postbyte */
|
#define SWI 0x3F
|
#define SWI 0x3F
|
|
|
/* register names */
|
/* register names */
|
|
|
#define RD 0
|
#define RD 0
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#define RX 1
|
#define RX 1
|
#define RY 2
|
#define RY 2
|
#define RU 3
|
#define RU 3
|
#define RS 4
|
#define RS 4
|
#define RPC 5
|
#define RPC 5
|
#define RA 8
|
#define RA 8
|
#define RB 9
|
#define RB 9
|
#define RCC 10
|
#define RCC 10
|
#define RDP 11
|
#define RDP 11
|
#define RPCR 12
|
#define RPCR 12
|
|
|
/* convert tfr/exg reg number into psh/pul format */
|
/* convert tfr/exg reg number into psh/pul format */
|
int regs[] = { 6,16,32,64,64,128,0,0,2,4,1,8,0};
|
int regs[] = { 6,16,32,64,64,128,0,0,2,4,1,8,0};
|
int rcycl[]= { 2,2, 2, 2, 2, 2, 0,0,1,1,1,1,0};
|
int rcycl[]= { 2,2, 2, 2, 2, 2, 0,0,1,1,1,1,0};
|
|
|
/* addressing modes */
|
/* addressing modes */
|
#define IMMED 0 /* immediate */
|
#define IMMED 0 /* immediate */
|
#define IND 1 /* indexed */
|
#define IND 1 /* indexed */
|
#define INDIR 2 /* indirect */
|
#define INDIR 2 /* indirect */
|
#define OTHER 3 /* NOTA */
|
#define OTHER 3 /* NOTA */
|
|
|
/*
|
/*
|
* localinit --- machine specific initialization
|
* localinit --- machine specific initialization
|
*/
|
*/
|
localinit()
|
localinit()
|
{
|
{
|
}
|
}
|
|
|
/*
|
/*
|
* do_op --- process mnemonic
|
* do_op --- process mnemonic
|
*
|
*
|
* Called with the base opcode and it's class. Optr points to
|
* Called with the base opcode and it's class. Optr points to
|
* the beginning of the operand field.
|
* the beginning of the operand field.
|
*/
|
*/
|
void do_op(int opcode,int class)
|
void do_op(int opcode,int class)
|
{
|
{
|
int dist; /* relative branch distance */
|
int dist; /* relative branch distance */
|
int src,dst;/* source and destination registers */
|
int src,dst;/* source and destination registers */
|
int pbyte; /* postbyte value */
|
int pbyte; /* postbyte value */
|
int amode; /* indicated addressing mode */
|
int amode; /* indicated addressing mode */
|
int j;
|
int j;
|
|
|
amode = set_mode(); /* pickup indicated addressing mode */
|
amode = set_mode(); /* pickup indicated addressing mode */
|
|
|
switch(class){
|
switch(class){
|
case INH: /* inherent addressing */
|
case INH: /* inherent addressing */
|
emit(opcode);
|
emit(opcode);
|
return;
|
return;
|
case GEN: /* general addressing */
|
case GEN: /* general addressing */
|
do_gen(opcode,amode);
|
do_gen(opcode,amode);
|
return;
|
return;
|
case IMM: /* immediate addressing */
|
case IMM: /* immediate addressing */
|
if( amode != IMMED ){
|
if( amode != IMMED ){
|
error("Immediate Operand Required");
|
error("Immediate Operand Required");
|
return;
|
return;
|
}
|
}
|
Optr++;
|
Optr++;
|
eval();
|
eval();
|
emit(opcode);
|
emit(opcode);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
return;
|
return;
|
case REL: /* short relative branches */
|
case REL: /* short relative branches */
|
eval();
|
eval();
|
dist = Result - (Pc+2);
|
dist = Result - (Pc+2);
|
emit(opcode);
|
emit(opcode);
|
if( (dist >127 || dist <-128) && Pass==2){
|
if( (dist >127 || dist <-128) && Pass==2){
|
error("Branch out of Range");
|
error("Branch out of Range");
|
emit(lobyte(-2));
|
emit(lobyte(-2));
|
return;
|
return;
|
}
|
}
|
emit(lobyte(dist));
|
emit(lobyte(dist));
|
return;
|
return;
|
case P2REL: /* long relative branches */
|
case P2REL: /* long relative branches */
|
eval();
|
eval();
|
dist = Result - (Pc+4);
|
dist = Result - (Pc+4);
|
emit(PAGE2);
|
emit(PAGE2);
|
emit(opcode);
|
emit(opcode);
|
eword(dist);
|
eword(dist);
|
return;
|
return;
|
case P1REL: /* lbra and lbsr */
|
case P1REL: /* lbra and lbsr */
|
if( amode == IMMED)
|
if( amode == IMMED)
|
Optr++; /* kludge for C compiler */
|
Optr++; /* kludge for C compiler */
|
eval();
|
eval();
|
dist = Result - (Pc+3);
|
dist = Result - (Pc+3);
|
emit(opcode);
|
emit(opcode);
|
eword(dist);
|
eword(dist);
|
return;
|
return;
|
case NOIMM:
|
case NOIMM:
|
if( amode == IMMED ){
|
if( amode == IMMED ){
|
error("Immediate Addressing Illegal");
|
error("Immediate Addressing Illegal");
|
return;
|
return;
|
}
|
}
|
do_gen(opcode,amode);
|
do_gen(opcode,amode);
|
return;
|
return;
|
case P2GEN:
|
case P2GEN:
|
emit(PAGE2);
|
emit(PAGE2);
|
if( amode == IMMED ){
|
if( amode == IMMED ){
|
emit(opcode);
|
emit(opcode);
|
Optr++;
|
Optr++;
|
eval();
|
eval();
|
eword(Result);
|
eword(Result);
|
return;
|
return;
|
}
|
}
|
do_gen(opcode,amode);
|
do_gen(opcode,amode);
|
return;
|
return;
|
case P3GEN:
|
case P3GEN:
|
emit(PAGE3);
|
emit(PAGE3);
|
if( amode == IMMED ){
|
if( amode == IMMED ){
|
emit(opcode);
|
emit(opcode);
|
Optr++;
|
Optr++;
|
eval();
|
eval();
|
eword(Result);
|
eword(Result);
|
return;
|
return;
|
}
|
}
|
do_gen(opcode,amode);
|
do_gen(opcode,amode);
|
return;
|
return;
|
case RTOR: /* tfr and exg */
|
case RTOR: /* tfr and exg */
|
emit(opcode);
|
emit(opcode);
|
src = regnum();
|
src = regnum();
|
while(alpha(*Optr))Optr++;
|
while(alpha(*Optr))Optr++;
|
if(src==ERR){
|
if(src==ERR){
|
error("Register Name Required");
|
error("Register Name Required");
|
emit(0);
|
emit(0);
|
return;
|
return;
|
}
|
}
|
if(*Optr++ != ','){
|
if(*Optr++ != ','){
|
error("Missing ,");
|
error("Missing ,");
|
emit(0);
|
emit(0);
|
return;
|
return;
|
}
|
}
|
dst = regnum();
|
dst = regnum();
|
while(alpha(*Optr))Optr++;
|
while(alpha(*Optr))Optr++;
|
if(dst==ERR){
|
if(dst==ERR){
|
error("Register Name Required");
|
error("Register Name Required");
|
emit(0);
|
emit(0);
|
return;
|
return;
|
}
|
}
|
if( src==RPCR || dst==RPCR){
|
if( src==RPCR || dst==RPCR){
|
error("PCR illegal here");
|
error("PCR illegal here");
|
emit(0);
|
emit(0);
|
return;
|
return;
|
}
|
}
|
if( (src <=5 && dst >=8) ||
|
if( (src <=5 && dst >=8) ||
|
(src >=8 && dst <=5)){
|
(src >=8 && dst <=5)){
|
error("Register Size Mismatch");
|
error("Register Size Mismatch");
|
emit(0);
|
emit(0);
|
return;
|
return;
|
}
|
}
|
emit( (src<<4)+dst );
|
emit( (src<<4)+dst );
|
return;
|
return;
|
case INDEXED: /* indexed addressing only */
|
case INDEXED: /* indexed addressing only */
|
if( *Optr == '#'){
|
if( *Optr == '#'){
|
Optr++; /* kludge city */
|
Optr++; /* kludge city */
|
amode = IND;
|
amode = IND;
|
}
|
}
|
if( amode != IND ){
|
if( amode != IND ){
|
error("Indexed Addressing Required");
|
error("Indexed Addressing Required");
|
return;
|
return;
|
}
|
}
|
do_indexed(opcode);
|
do_indexed(opcode);
|
return;
|
return;
|
case RLIST: /* pushes and pulls */
|
case RLIST: /* pushes and pulls */
|
if(*Operand == EOS){
|
if(*Operand == EOS){
|
error("Register List Required");
|
error("Register List Required");
|
return;
|
return;
|
}
|
}
|
emit(opcode);
|
emit(opcode);
|
pbyte = 0;
|
pbyte = 0;
|
do{
|
do{
|
j = regnum();
|
j = regnum();
|
if( j == ERR || j==RPCR)
|
if( j == ERR || j==RPCR)
|
error("Illegal Register Name");
|
error("Illegal Register Name");
|
else if(j==RS && (opcode==52))
|
else if(j==RS && (opcode==52))
|
error("Can't Push S on S");
|
error("Can't Push S on S");
|
else if(j==RU && (opcode==54))
|
else if(j==RU && (opcode==54))
|
error("Can't Push U on U");
|
error("Can't Push U on U");
|
else if(j==RS && (opcode==53))
|
else if(j==RS && (opcode==53))
|
error("Can't Pull S from S");
|
error("Can't Pull S from S");
|
else if(j==RU && (opcode==55))
|
else if(j==RU && (opcode==55))
|
error("Can't Pull U from U");
|
error("Can't Pull U from U");
|
else{
|
else{
|
pbyte |= regs[j];
|
pbyte |= regs[j];
|
Cycles += rcycl[j];
|
Cycles += rcycl[j];
|
}
|
}
|
while(*Optr != EOS && alpha(*Optr))Optr++;
|
while(*Optr != EOS && alpha(*Optr))Optr++;
|
}while( *Optr++ == ',' );
|
}while( *Optr++ == ',' );
|
emit(lobyte(pbyte));
|
emit(lobyte(pbyte));
|
return;
|
return;
|
case P2NOIMM:
|
case P2NOIMM:
|
if( amode == IMMED )
|
if( amode == IMMED )
|
error("Immediate Addressing Illegal");
|
error("Immediate Addressing Illegal");
|
else{
|
else{
|
emit(PAGE2);
|
emit(PAGE2);
|
do_gen(opcode,amode);
|
do_gen(opcode,amode);
|
}
|
}
|
return;
|
return;
|
case P2INH: /* Page 2 inherent */
|
case P2INH: /* Page 2 inherent */
|
emit(PAGE2);
|
emit(PAGE2);
|
emit(opcode);
|
emit(opcode);
|
return;
|
return;
|
case P3INH: /* Page 3 inherent */
|
case P3INH: /* Page 3 inherent */
|
emit(PAGE3);
|
emit(PAGE3);
|
emit(opcode);
|
emit(opcode);
|
return;
|
return;
|
case LONGIMM:
|
case LONGIMM:
|
if( amode == IMMED ){
|
if( amode == IMMED ){
|
emit(opcode);
|
emit(opcode);
|
Optr++;
|
Optr++;
|
eval();
|
eval();
|
eword(Result);
|
eword(Result);
|
}
|
}
|
else
|
else
|
do_gen(opcode,amode);
|
do_gen(opcode,amode);
|
return;
|
return;
|
case GRP2:
|
case GRP2:
|
if( amode == IND ){
|
if( amode == IND ){
|
do_indexed(opcode+0x60);
|
do_indexed(opcode+0x60);
|
return;
|
return;
|
}
|
}
|
else if( amode == INDIR){
|
else if( amode == INDIR){
|
Optr++;
|
Optr++;
|
emit(opcode + 0x60);
|
emit(opcode + 0x60);
|
emit(IPBYTE);
|
emit(IPBYTE);
|
eval();
|
eval();
|
eword(Result);
|
eword(Result);
|
Cycles += 7;
|
Cycles += 7;
|
if(*Optr == ']'){
|
if(*Optr == ']'){
|
Optr++;
|
Optr++;
|
return;
|
return;
|
}
|
}
|
error("Missing ']'");
|
error("Missing ']'");
|
return;
|
return;
|
}
|
}
|
eval();
|
eval();
|
if(Force_word){
|
if(Force_word){
|
emit(opcode+0x70);
|
emit(opcode+0x70);
|
eword(Result);
|
eword(Result);
|
Cycles += 3;
|
Cycles += 3;
|
return;
|
return;
|
}
|
}
|
if(Force_byte){
|
if(Force_byte){
|
emit(opcode);
|
emit(opcode);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles += 2;
|
Cycles += 2;
|
return;
|
return;
|
}
|
}
|
if(Result>=0 && Result <=0xFF){
|
if(Result>=0 && Result <=0xFF){
|
emit(opcode);
|
emit(opcode);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles += 2;
|
Cycles += 2;
|
return;
|
return;
|
}
|
}
|
else {
|
else {
|
emit(opcode+0x70);
|
emit(opcode+0x70);
|
eword(Result);
|
eword(Result);
|
Cycles += 3;
|
Cycles += 3;
|
return;
|
return;
|
}
|
}
|
case SYS: /* system call */
|
case SYS: /* system call */
|
emit(SWI);
|
emit(SWI);
|
eval();
|
eval();
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
return;
|
return;
|
default:
|
default:
|
fatal("Error in Mnemonic table");
|
fatal("Error in Mnemonic table");
|
}
|
}
|
}
|
}
|
|
|
|
|
/*
|
/*
|
* do_gen --- process general addressing mode stuff
|
* do_gen --- process general addressing mode stuff
|
*/
|
*/
|
do_gen(op,mode)
|
do_gen(op,mode)
|
int op;
|
int op;
|
int mode;
|
int mode;
|
{
|
{
|
if( mode == IMMED){
|
if( mode == IMMED){
|
Optr++;
|
Optr++;
|
emit(op);
|
emit(op);
|
eval();
|
eval();
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
return(0);
|
return(0);
|
}
|
}
|
else if( mode == IND ){
|
else if( mode == IND ){
|
do_indexed(op+0x20);
|
do_indexed(op+0x20);
|
return(0);
|
return(0);
|
}
|
}
|
else if( mode == INDIR){
|
else if( mode == INDIR){
|
Optr++;
|
Optr++;
|
emit(op+0x20);
|
emit(op+0x20);
|
emit(IPBYTE);
|
emit(IPBYTE);
|
eval();
|
eval();
|
eword(Result);
|
eword(Result);
|
Cycles += 7;
|
Cycles += 7;
|
if(*Optr == ']'){
|
if(*Optr == ']'){
|
Optr++;
|
Optr++;
|
return(0);
|
return(0);
|
}
|
}
|
error("Missing ']'");
|
error("Missing ']'");
|
return(0);
|
return(0);
|
}
|
}
|
else if( mode == OTHER){
|
else if( mode == OTHER){
|
eval();
|
eval();
|
if(Force_word){
|
if(Force_word){
|
emit(op+0x30);
|
emit(op+0x30);
|
eword(Result);
|
eword(Result);
|
Cycles += 3;
|
Cycles += 3;
|
return(0);
|
return(0);
|
}
|
}
|
if(Force_byte){
|
if(Force_byte){
|
emit(op+0x10);
|
emit(op+0x10);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles += 2;
|
Cycles += 2;
|
return(0);
|
return(0);
|
}
|
}
|
if(Result>=0 && Result <=0xFF){
|
if(Result>=0 && Result <=0xFF){
|
emit(op+0x10);
|
emit(op+0x10);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles += 2;
|
Cycles += 2;
|
return(0);
|
return(0);
|
}
|
}
|
else {
|
else {
|
emit(op+0x30);
|
emit(op+0x30);
|
eword(Result);
|
eword(Result);
|
Cycles += 3;
|
Cycles += 3;
|
return(0);
|
return(0);
|
}
|
}
|
}
|
}
|
else {
|
else {
|
error("Unknown Addressing Mode");
|
error("Unknown Addressing Mode");
|
return(0);
|
return(0);
|
}
|
}
|
}
|
}
|
|
|
/*
|
/*
|
* do_indexed --- handle all wierd stuff for indexed addressing
|
* do_indexed --- handle all wierd stuff for indexed addressing
|
*/
|
*/
|
do_indexed(op)
|
do_indexed(op)
|
int op;
|
int op;
|
{
|
{
|
int pbyte;
|
int pbyte;
|
int j,k;
|
int j,k;
|
int predec,pstinc;
|
int predec,pstinc;
|
|
|
Cycles += 2; /* indexed is always 2+ base cycle count */
|
Cycles += 2; /* indexed is always 2+ base cycle count */
|
predec=0;
|
predec=0;
|
pstinc=0;
|
pstinc=0;
|
pbyte=128;
|
pbyte=128;
|
emit(op);
|
emit(op);
|
if(*Optr=='['){
|
if(*Optr=='['){
|
pbyte |= 0x10; /* set indirect bit */
|
pbyte |= 0x10; /* set indirect bit */
|
Optr++;
|
Optr++;
|
if( !any((char)']',Optr))
|
if( !any((char)']',Optr))
|
error("Missing ']'");
|
error("Missing ']'");
|
Cycles += 3; /* indirection takes this much longer */
|
Cycles += 3; /* indirection takes this much longer */
|
}
|
}
|
j=regnum();
|
j=regnum();
|
if(j==RA){
|
if(j==RA){
|
Cycles++;
|
Cycles++;
|
abd_index(pbyte+6);
|
abd_index(pbyte+6);
|
return(0);
|
return(0);
|
}
|
}
|
if(j==RB){
|
if(j==RB){
|
Cycles++;
|
Cycles++;
|
abd_index(pbyte+5);
|
abd_index(pbyte+5);
|
return(0);
|
return(0);
|
}
|
}
|
if(j==RD){
|
if(j==RD){
|
Cycles += 4;
|
Cycles += 4;
|
abd_index(pbyte+11);
|
abd_index(pbyte+11);
|
return(0);
|
return(0);
|
}
|
}
|
eval();
|
eval();
|
Optr++;
|
Optr++;
|
while(*Optr=='-'){
|
while(*Optr=='-'){
|
predec++;
|
predec++;
|
Optr++;
|
Optr++;
|
}
|
}
|
j=regnum();
|
j=regnum();
|
while( alpha(*Optr) )Optr++;
|
while( alpha(*Optr) )Optr++;
|
while(*Optr=='+'){
|
while(*Optr=='+'){
|
pstinc++;
|
pstinc++;
|
Optr++;
|
Optr++;
|
}
|
}
|
if(j==RPC || j==RPCR){
|
if(j==RPC || j==RPCR){
|
if( pstinc || predec ){
|
if( pstinc || predec ){
|
error("Auto Inc/Dec Illegal on PC");
|
error("Auto Inc/Dec Illegal on PC");
|
return(0);
|
return(0);
|
}
|
}
|
if(j==RPC){
|
if(j==RPC){
|
if(Force_word){
|
if(Force_word){
|
emit(pbyte+13);
|
emit(pbyte+13);
|
eword(Result);
|
eword(Result);
|
Cycles += 5;
|
Cycles += 5;
|
return(0);
|
return(0);
|
}
|
}
|
if(Force_byte){
|
if(Force_byte){
|
emit(pbyte+12);
|
emit(pbyte+12);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
if(Result>=-128 && Result <=127){
|
if(Result>=-128 && Result <=127){
|
emit(pbyte+12);
|
emit(pbyte+12);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
else {
|
else {
|
emit(pbyte+13);
|
emit(pbyte+13);
|
eword(Result);
|
eword(Result);
|
Cycles += 5;
|
Cycles += 5;
|
return(0);
|
return(0);
|
}
|
}
|
}
|
}
|
/* PCR addressing */
|
/* PCR addressing */
|
if(Force_word){
|
if(Force_word){
|
emit(pbyte+13);
|
emit(pbyte+13);
|
eword(Result-(Pc+2));
|
eword(Result-(Pc+2));
|
Cycles += 5;
|
Cycles += 5;
|
return(0);
|
return(0);
|
}
|
}
|
if(Force_byte){
|
if(Force_byte){
|
emit(pbyte+12);
|
emit(pbyte+12);
|
emit(lobyte(Result-(Pc+1)));
|
emit(lobyte(Result-(Pc+1)));
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
k=Result-(Pc+2);
|
k=Result-(Pc+2);
|
if( k >= -128 && k <= 127){
|
if( k >= -128 && k <= 127){
|
emit(pbyte+12);
|
emit(pbyte+12);
|
emit(lobyte(Result-(Pc+1)));
|
emit(lobyte(Result-(Pc+1)));
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
else{
|
else{
|
emit(pbyte+13);
|
emit(pbyte+13);
|
eword(Result-(Pc+2));
|
eword(Result-(Pc+2));
|
Cycles += 5;
|
Cycles += 5;
|
return(0);
|
return(0);
|
}
|
}
|
}
|
}
|
if(predec || pstinc){
|
if(predec || pstinc){
|
if(Result != 0){
|
if(Result != 0){
|
error("Offset must be Zero");
|
error("Offset must be Zero");
|
return(0);
|
return(0);
|
}
|
}
|
if(predec>2 || pstinc>2){
|
if(predec>2 || pstinc>2){
|
error("Auto Inc/Dec by 1 or 2 only");
|
error("Auto Inc/Dec by 1 or 2 only");
|
return(0);
|
return(0);
|
}
|
}
|
if((predec==1 && (pbyte&0x10) != 0) ||
|
if((predec==1 && (pbyte&0x10) != 0) ||
|
(pstinc==1 && (pbyte&0x10) != 0)){
|
(pstinc==1 && (pbyte&0x10) != 0)){
|
error("No Auto Inc/Dec by 1 for Indirect");
|
error("No Auto Inc/Dec by 1 for Indirect");
|
return(0);
|
return(0);
|
}
|
}
|
if(predec && pstinc){
|
if(predec && pstinc){
|
error("Can't do both!");
|
error("Can't do both!");
|
return(0);
|
return(0);
|
}
|
}
|
if(predec)
|
if(predec)
|
pbyte += predec+1;
|
pbyte += predec+1;
|
if(pstinc)
|
if(pstinc)
|
pbyte += pstinc-1;
|
pbyte += pstinc-1;
|
pbyte += rtype(j);
|
pbyte += rtype(j);
|
emit(pbyte);
|
emit(pbyte);
|
Cycles += 1 + predec + pstinc;
|
Cycles += 1 + predec + pstinc;
|
return(0);
|
return(0);
|
}
|
}
|
pbyte += rtype(j);
|
pbyte += rtype(j);
|
if(Force_word){
|
if(Force_word){
|
emit(pbyte+0x09);
|
emit(pbyte+0x09);
|
eword(Result);
|
eword(Result);
|
Cycles += 4;
|
Cycles += 4;
|
return(0);
|
return(0);
|
}
|
}
|
if(Force_byte){
|
if(Force_byte){
|
emit(pbyte+0x08);
|
emit(pbyte+0x08);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
if(Result==0){
|
if(Result==0){
|
emit(pbyte+0x04);
|
emit(pbyte+0x04);
|
return(0);
|
return(0);
|
}
|
}
|
if((Result >= -16) && (Result <= 15) && ((pbyte&16)==0)){
|
if((Result >= -16) && (Result <= 15) && ((pbyte&16)==0)){
|
pbyte &= 127;
|
pbyte &= 127;
|
pbyte += Result&31;
|
pbyte += Result&31;
|
emit(pbyte);
|
emit(pbyte);
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
if(Result >= -128 && Result <= 127){
|
if(Result >= -128 && Result <= 127){
|
emit(pbyte+0x08);
|
emit(pbyte+0x08);
|
emit(lobyte(Result));
|
emit(lobyte(Result));
|
Cycles++;
|
Cycles++;
|
return(0);
|
return(0);
|
}
|
}
|
emit(pbyte+0x09);
|
emit(pbyte+0x09);
|
eword(Result);
|
eword(Result);
|
Cycles += 4;
|
Cycles += 4;
|
return(0);
|
return(0);
|
}
|
}
|
|
|
|
|
/*
|
/*
|
* abd_index --- a,b or d indexed
|
* abd_index --- a,b or d indexed
|
*/
|
*/
|
|
|
abd_index(pbyte)
|
abd_index(pbyte)
|
int pbyte;
|
int pbyte;
|
{
|
{
|
int k;
|
int k;
|
|
|
Optr += 2;
|
Optr += 2;
|
k=regnum();
|
k=regnum();
|
pbyte += rtype(k);
|
pbyte += rtype(k);
|
emit(pbyte);
|
emit(pbyte);
|
return(0);
|
return(0);
|
}
|
}
|
|
|
/*
|
/*
|
* rtype --- return register type in post-byte format
|
* rtype --- return register type in post-byte format
|
*/
|
*/
|
rtype(r)
|
rtype(r)
|
int r;
|
int r;
|
{
|
{
|
switch(r){
|
switch(r){
|
case RX: return(0x00);
|
case RX: return(0x00);
|
case RY: return(0x20);
|
case RY: return(0x20);
|
case RU: return(0x40);
|
case RU: return(0x40);
|
case RS: return(0x60);
|
case RS: return(0x60);
|
}
|
}
|
error("Illegal Register for Indexed");
|
error("Illegal Register for Indexed");
|
return(0);
|
return(0);
|
}
|
}
|
|
|
/*
|
/*
|
* set_mode --- determine addressing mode from operand field
|
* set_mode --- determine addressing mode from operand field
|
*/
|
*/
|
set_mode()
|
set_mode()
|
{
|
{
|
register char *p;
|
register char *p;
|
|
|
if( *Operand == '#' )
|
if( *Operand == '#' )
|
return(IMMED); /* immediate addressing */
|
return(IMMED); /* immediate addressing */
|
p = Operand;
|
p = Operand;
|
while( *p != EOS && *p != BLANK && *p != TAB){/* any , before break */
|
while( *p != EOS && *p != BLANK && *p != TAB){/* any , before break */
|
if( *p == ',')
|
if( *p == ',')
|
return(IND); /* indexed addressing */
|
return(IND); /* indexed addressing */
|
p++;
|
p++;
|
}
|
}
|
if( *Operand == '[')
|
if( *Operand == '[')
|
return(INDIR); /* indirect addressing */
|
return(INDIR); /* indirect addressing */
|
return(OTHER); /* NOTA */
|
return(OTHER); /* NOTA */
|
}
|
}
|
|
|
/*
|
/*
|
* regnum --- return register number of *Optr
|
* regnum --- return register number of *Optr
|
*/
|
*/
|
regnum()
|
regnum()
|
{
|
{
|
if( head(Optr,"D" ))return(RD);
|
if( head(Optr,"D" ))return(RD);
|
if( head(Optr,"d" ))return(RD);
|
if( head(Optr,"d" ))return(RD);
|
if( head(Optr,"X" ))return(RX);
|
if( head(Optr,"X" ))return(RX);
|
if( head(Optr,"x" ))return(RX);
|
if( head(Optr,"x" ))return(RX);
|
if( head(Optr,"Y" ))return(RY);
|
if( head(Optr,"Y" ))return(RY);
|
if( head(Optr,"y" ))return(RY);
|
if( head(Optr,"y" ))return(RY);
|
if( head(Optr,"U" ))return(RU);
|
if( head(Optr,"U" ))return(RU);
|
if( head(Optr,"u" ))return(RU);
|
if( head(Optr,"u" ))return(RU);
|
if( head(Optr,"S" ))return(RS);
|
if( head(Optr,"S" ))return(RS);
|
if( head(Optr,"s" ))return(RS);
|
if( head(Optr,"s" ))return(RS);
|
if( head(Optr,"PC" ))return(RPC);
|
if( head(Optr,"PC" ))return(RPC);
|
if( head(Optr,"pc" ))return(RPC);
|
if( head(Optr,"pc" ))return(RPC);
|
if( head(Optr,"PCR" ))return(RPCR);
|
if( head(Optr,"PCR" ))return(RPCR);
|
if( head(Optr,"pcr" ))return(RPCR);
|
if( head(Optr,"pcr" ))return(RPCR);
|
if( head(Optr,"A" ))return(RA);
|
if( head(Optr,"A" ))return(RA);
|
if( head(Optr,"a" ))return(RA);
|
if( head(Optr,"a" ))return(RA);
|
if( head(Optr,"B" ))return(RB);
|
if( head(Optr,"B" ))return(RB);
|
if( head(Optr,"b" ))return(RB);
|
if( head(Optr,"b" ))return(RB);
|
if( head(Optr,"CC" ))return(RCC);
|
if( head(Optr,"CC" ))return(RCC);
|
if( head(Optr,"cc" ))return(RCC);
|
if( head(Optr,"cc" ))return(RCC);
|
if( head(Optr,"DP" ))return(RDP);
|
if( head(Optr,"DP" ))return(RDP);
|
if( head(Optr,"dp" ))return(RDP);
|
if( head(Optr,"dp" ))return(RDP);
|
return(ERR);
|
return(ERR);
|
}
|
}
|
|
|
|
|
|
|
